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MIR: remove explicit "noVRegs" property. 

We can infer this from the incoming MIR, so there's no reason to
represent it with a special flag.

llvm-svn: 304246
This commit is contained in:
Tim Northover 2017-05-30 21:28:57 +00:00
parent 74480adafd
commit fb26d9a286
10 changed files with 0 additions and 14 deletions
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2
llvm/include/llvm/CodeGen/MIRYamlMapping.h
View File

@ -381,7 +381,6 @@ struct MachineFunction {
StringRef Name;
unsigned Alignment = 0;
bool ExposesReturnsTwice = false;
bool NoVRegs;
// GISel MachineFunctionProperties.
bool Legalized = false;
bool RegBankSelected = false;
@ -406,7 +405,6 @@ template <> struct MappingTraits<MachineFunction> {
YamlIO.mapRequired("name", MF.Name);
YamlIO.mapOptional("alignment", MF.Alignment);
YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
YamlIO.mapOptional("noVRegs", MF.NoVRegs);
YamlIO.mapOptional("legalized", MF.Legalized);
YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
YamlIO.mapOptional("selected", MF.Selected);

2
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
View File

@ -332,8 +332,6 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
MF.setAlignment(YamlMF.Alignment);
MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
if (YamlMF.NoVRegs)
MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
if (YamlMF.Legalized)
MF.getProperties().set(MachineFunctionProperties::Property::Legalized);
if (YamlMF.RegBankSelected)

2
llvm/lib/CodeGen/MIRPrinter.cpp
View File

@ -183,8 +183,6 @@ void MIRPrinter::print(const MachineFunction &MF) {
YamlMF.Alignment = MF.getAlignment();
YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
YamlMF.NoVRegs = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::NoVRegs);
YamlMF.Legalized = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::Legalized);
YamlMF.RegBankSelected = MF.getProperties().hasProperty(

1
llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
View File

@ -13,7 +13,6 @@
name: main
alignment: 2
exposesReturnsTwice: false
noVRegs: false
legalized: true
regBankSelected: true
selected: false

1
llvm/test/CodeGen/AMDGPU/merge-m0.mir
View File

@ -50,7 +50,6 @@
name: test
alignment: 0
exposesReturnsTwice: false
noVRegs: false
legalized: false
regBankSelected: false
selected: false

2
llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir
View File

@ -190,7 +190,6 @@
name: foo
alignment: 1
exposesReturnsTwice: false
noVRegs: true
legalized: false
regBankSelected: false
selected: false
@ -289,7 +288,6 @@ body: |
name: bar
alignment: 1
exposesReturnsTwice: false
noVRegs: true
legalized: false
regBankSelected: false
selected: false

1
llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
View File

@ -39,7 +39,6 @@
name: l5
alignment: 2
exposesReturnsTwice: false
noVRegs: true
legalized: false
regBankSelected: false
selected: false

1
llvm/test/CodeGen/Thumb2/tbb-removeadd.mir
View File

@ -39,7 +39,6 @@
name: Func
alignment: 1
exposesReturnsTwice: false
noVRegs: true
legalized: false
regBankSelected: false
selected: false

1
llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll
View File

@ -5,7 +5,6 @@ define void @test_void_return() {
; CHECK-LABEL: name: test_void_return
; CHECK: alignment: 4
; CHECK-NEXT: exposesReturnsTwice: false
; CHECK-NEXT: noVRegs: false
; CHECK-NEXT: legalized: false
; CHECK-NEXT: regBankSelected: false
; CHECK-NEXT: selected: false

1
llvm/test/DebugInfo/MIR/X86/empty-inline.mir
View File

@ -73,7 +73,6 @@
name: _ZN1C5m_fn3Ev
alignment: 4
exposesReturnsTwice: false
noVRegs: true
legalized: false
regBankSelected: false
selected: false