diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h index eb6d3651d647..63bb8b275861 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h @@ -16,7 +16,6 @@ #define LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H #include "llvm/ADT/APInt.h" -#include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/GlobalISel/RegisterBank.h" #include "llvm/CodeGen/GlobalISel/Types.h" #include "llvm/Support/ErrorHandling.h" @@ -96,17 +95,11 @@ public: /// The rationale is that it is more efficient for the optimizers /// to be able to assume that the mapping of the ith operand is /// at the index i. - /// - /// \pre ID != InvalidMappingID InstructionMapping(unsigned ID, unsigned Cost, unsigned NumOperands) : ID(ID), Cost(Cost), NumOperands(NumOperands) { OperandsMapping.reset(new ValueMapping[getNumOperands()]); } - /// Default constructor. - /// Use this constructor to express that the mapping is invalid. - InstructionMapping() : InstructionMapping(InvalidMappingID, 0, 0) {} - /// Get the cost. unsigned getCost() const { return Cost; } @@ -126,19 +119,10 @@ public: getOperandMapping(i) = ValMapping; } - /// Check whether this object is valid. - /// This is a lightweight check for obvious wrong instance. - bool isValid() const { return getID() != InvalidMappingID; } - /// Verifiy that this mapping makes sense for \p MI. void verify(const MachineInstr &MI) const; }; - /// Convenient type to represent the alternatives for mapping an - /// instruction. - /// \todo When we move to TableGen this should be an array ref. - typedef SmallVector InstructionMappings; - protected: /// Hold the set of supported register banks. std::unique_ptr RegBanks; @@ -229,74 +213,6 @@ public: return 0; } - /// Identifier used when the related instruction mapping instance - /// is generated by target independent code. - /// Make sure not to use that identifier to avoid possible collision. - static const unsigned DefaultMappingID; - - /// Identifier used when the related instruction mapping instance - /// is generated by the default constructor. - /// Make sure not to use that identifier. - static const unsigned InvalidMappingID; - - /// Get the mapping of the different operands of \p MI - /// on the register bank. - /// This mapping should be the direct translation of \p MI. - /// The target independent implementation gives a mapping based on - /// the register classes for the target specific opcode. - /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping. - /// Make sure you do not use that ID for the alternative mapping - /// for MI. See getInstrAlternativeMappings for the alternative - /// mappings. - /// - /// For instance, if \p MI is a vector add, the mapping should - /// not be a scalarization of the add. - /// - /// \post returnedVal.verify(MI). - /// - /// \note If returnedVal does not verify MI, this would probably mean - /// that the target does not support that instruction. - virtual InstructionMapping getInstrMapping(const MachineInstr &MI) const; - - /// Get the alternative mappings for \p MI. - /// Alternative in the sense different from getInstrMapping. - virtual InstructionMappings - getInstrAlternativeMappings(const MachineInstr &MI) const { - // No alternative for MI. - return InstructionMappings(); - } - - /// Get the possible mapping for \p MI. - /// A mapping defines where the different operands may live and at what cost. - /// For instance, let us consider: - /// v0(16) = G_ADD <2 x i8> v1, v2 - /// The possible mapping could be: - /// - /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)}, - /// /*v2*/{(0xFFFF, VPR)}} - /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)}, - /// /*v1*/{(0x00FF, GPR),(0xFF00, GPR)}, - /// /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}} - /// - /// \note The first alternative of the returned mapping should be the - /// direct translation of \p MI current form. - /// - /// \post !returnedVal.empty(). - InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const { - InstructionMappings PossibleMappings; - // Put the default mapping first. - PossibleMappings.push_back(getInstrMapping(MI)); - // Then the alternative mapping, if any. - InstructionMappings AltMappings = getInstrAlternativeMappings(MI); - for (InstructionMapping &AltMapping : AltMappings) - PossibleMappings.emplace_back(std::move(AltMapping)); -#ifndef NDEBUG - for (const InstructionMapping &Mapping : PossibleMappings) - Mapping.verify(MI); -#endif - return PossibleMappings; - } - void verify(const TargetRegisterInfo &TRI) const; }; diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp index 8287a15e01dd..6e8307917c78 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -19,9 +19,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetOpcodes.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Target/TargetSubtargetInfo.h" #include // For std::max. @@ -29,40 +27,6 @@ using namespace llvm; -const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX; -const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1; - -/// Get the size in bits of the \p OpIdx-th operand of \p MI. -/// -/// \pre \p MI is part of a basic block and this basic block is part -/// of a function. -static unsigned getSizeInBits(const MachineInstr &MI, unsigned OpIdx) { - unsigned Reg = MI.getOperand(OpIdx).getReg(); - const TargetRegisterClass *RC = nullptr; - if (TargetRegisterInfo::isPhysicalRegister(Reg)) { - const TargetSubtargetInfo &STI = - MI.getParent()->getParent()->getSubtarget(); - const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); - // The size is not directly available for physical registers. - // Instead, we need to access a register class that contains Reg and - // get the size of that register class. - RC = TRI.getMinimalPhysRegClass(Reg); - } else { - const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); - unsigned RegSize = MRI.getSize(Reg); - // If Reg is not a generic register, query the register class to - // get its size. - if (RegSize) - return RegSize; - RC = MRI.getRegClass(Reg); - } - assert(RC && "Unable to deduce the register class"); - return RC->getSize() * 8; -} - -//------------------------------------------------------------------------------ -// RegisterBankInfo implementation. -//------------------------------------------------------------------------------ RegisterBankInfo::RegisterBankInfo(unsigned NumRegBanks) : NumRegBanks(NumRegBanks) { RegBanks.reset(new RegisterBank[NumRegBanks]); @@ -212,14 +176,6 @@ void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned RCId, } while (!WorkList.empty()); } -RegisterBankInfo::InstructionMapping -RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { - if (MI.getOpcode() > TargetOpcode::GENERIC_OP_END) { - // TODO. - } - llvm_unreachable("The target must implement this"); -} - //------------------------------------------------------------------------------ // Helper classes implementation. //------------------------------------------------------------------------------ @@ -278,6 +234,7 @@ void RegisterBankInfo::ValueMapping::verify(unsigned ExpectedBitWidth) const { void RegisterBankInfo::InstructionMapping::verify( const MachineInstr &MI) const { // Check that all the register operands are properly mapped. + const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); // Check the constructor invariant. assert(NumOperands == MI.getNumOperands() && "NumOperands must match, see constructor"); @@ -289,9 +246,14 @@ void RegisterBankInfo::InstructionMapping::verify( "We should not care about non-reg mapping"); continue; } + unsigned Reg = MO.getReg(); // Register size in bits. - // This size must match what the mapping expects. - unsigned RegSize = getSizeInBits(MI, Idx); + // This size must match what the mapping expect. + unsigned RegSize = MRI.getSize(Reg); + // If Reg is not a generic register, query the register class to + // get its size. + if (!RegSize) + RegSize = MRI.getRegClass(Reg)->getSize() * 8; MOMapping.verify(RegSize); } }