maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Remove unused HasFROperands field from disassembler. 

llvm-svn: 198332
This commit is contained in:
Craig Topper 2014-01-02 18:44:21 +00:00
parent d1b760a670
commit fae226c67e
2 changed files with 0 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
llvm/utils/TableGen/X86RecognizableInstr.cpp
View File

@ -256,7 +256,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
(Name.find("CRC32") != Name.npos);
HasFROperands = hasFROperands();
HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
// Check for 64-bit inst which does not require REX
@ -539,19 +538,6 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const {
return FILTER_NORMAL;
}
bool RecognizableInstr::hasFROperands() const {
const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
unsigned numOperands = OperandList.size();
for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
const std::string &recName = OperandList[operandIndex].Rec->getName();
if (recName.find("FR") != recName.npos)
return true;
}
return false;
}
void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
unsigned &physicalOperandIndex,
unsigned &numPhysicalOperands,

3
llvm/utils/TableGen/X86RecognizableInstr.h
View File

@ -92,9 +92,6 @@ private:
/// Indicates whether the instruction is SSE
bool IsSSE;
/// Indicates whether the instruction has FR operands - MOVs with FR operands
/// are typically ignored
bool HasFROperands;
/// Indicates whether the instruction should be emitted into the decode
/// tables; regardless, it will be emitted into the instruction info table
bool ShouldBeEmitted;