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[RISCV] Minor code/comment improvement in prepass of InsertVSETVLI [nfc]

This commit is contained in:
Philip Reames 2022-06-14 16:15:26 -07:00 committed by Philip Reames
parent 98fe869373
commit facb96584e
1 changed files with 14 additions and 21 deletions
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35
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
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@ -1213,17 +1213,22 @@ void RISCVInsertVSETVLI::doLocalPrepass(MachineBasicBlock &MBB) {
if (RISCVII::hasSEWOp(TSFlags)) { if (RISCVII::hasSEWOp(TSFlags)) {
if (RISCVII::hasVLOp(TSFlags)) { if (RISCVII::hasVLOp(TSFlags)) {
const auto Require = computeInfoForInstr(MI, TSFlags, MRI); const auto Require = computeInfoForInstr(MI, TSFlags, MRI);
// If the AVL is the result of a previous vsetvli which has the // Two cases involving an AVL resulting from a previous vsetvli.
// same AVL and VLMAX as our current state, we can reuse the AVL // 1) If the AVL is the result of a previous vsetvli which has the
// from the current state for the new one. This allows us to // same AVL and VLMAX as our current state, we can reuse the AVL
// generate 'vsetvli x0, x0, vtype" or possible skip the transition // from the current state for the new one. This allows us to
// entirely. // generate 'vsetvli x0, x0, vtype" or possible skip the transition
if (!CurInfo.isUnknown() && Require.hasAVLReg() && // entirely.
Require.getAVLReg().isVirtual()) { // 2) If AVL is defined by a vsetvli with the same VLMAX, we can
// replace the AVL operand with the AVL of the defining vsetvli.
// We avoid general register AVLs to avoid extending live ranges
// without being sure we can kill the original source reg entirely.
if (Require.hasAVLReg() && Require.getAVLReg().isVirtual()) {
if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) { if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) {
if (isVectorConfigInstr(*DefMI)) { if (isVectorConfigInstr(*DefMI)) {
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI); VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
if (DefInfo.hasSameAVL(CurInfo) && // case 1
if (!CurInfo.isUnknown() && DefInfo.hasSameAVL(CurInfo) &&
DefInfo.hasSameVLMAX(CurInfo)) { DefInfo.hasSameVLMAX(CurInfo)) {
MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI)); MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));
if (CurInfo.hasAVLImm()) if (CurInfo.hasAVLImm())
@ -1235,19 +1240,7 @@ void RISCVInsertVSETVLI::doLocalPrepass(MachineBasicBlock &MBB) {
CurInfo = computeInfoForInstr(MI, TSFlags, MRI); CurInfo = computeInfoForInstr(MI, TSFlags, MRI);
continue; continue;
} }
} // case 2
}
}
// If AVL is defined by a vsetvli with the same VLMAX, we can
// replace the AVL operand with the AVL of the defining vsetvli.
// We avoid general register AVLs to avoid extending live ranges
// without being sure we can kill the original source reg entirely.
// TODO: We can ignore policy bits here, we only need VL to be the same.
if (Require.hasAVLReg() && Require.getAVLReg().isVirtual()) {
if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) {
if (isVectorConfigInstr(*DefMI)) {
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
if (DefInfo.hasSameVLMAX(Require) && if (DefInfo.hasSameVLMAX(Require) &&
(DefInfo.hasAVLImm() || DefInfo.getAVLReg() == RISCV::X0)) { (DefInfo.hasAVLImm() || DefInfo.getAVLReg() == RISCV::X0)) {
MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI)); MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));