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Fix the LLC regressions on X86 last night. In particular, when undoing 

previous copy elisions and we discover we need to reload a register, make
sure to use the regclass of the original register for the reload, not the
class of the current register.  This avoid using 16-bit loads to reload 32-bit
values.

llvm-svn: 23645
This commit is contained in:
Chris Lattner 2005-10-06 17:19:06 +00:00
parent e4c91fc9e8
commit fabe55f155
1 changed files with 11 additions and 4 deletions
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15
llvm/lib/CodeGen/VirtRegMap.cpp
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@ -266,9 +266,14 @@ namespace {
// AssignedPhysReg - The physreg that was assigned for use by the reload.
unsigned AssignedPhysReg;
// VirtReg - The virtual register itself.
unsigned VirtReg;
ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr)
: Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr) {}
ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
unsigned vreg)
: Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
VirtReg(vreg) {}
};
}
@ -381,7 +386,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
// case, we actually insert a reload for V1 in R1, ensuring that
// we can get at R0 or its alias.
ReusedOperands.push_back(ReusedOp(i, StackSlot, PhysReg,
VRM.getPhys(VirtReg)));
VRM.getPhys(VirtReg), VirtReg));
++NumReused;
continue;
}
@ -409,8 +414,10 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
// Okay, we found out that an alias of a reused register
// was used. This isn't good because it means we have
// to undo a previous reuse.
const TargetRegisterClass *AliasRC =
MBB.getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
Op.StackSlot, RC);
Op.StackSlot, AliasRC);
ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
PhysRegsAvailable);