diff --git a/llvm/test/CodeGen/AMDGPU/kernel-args.ll b/llvm/test/CodeGen/AMDGPU/kernel-args.ll index 64a5fbdf00aa..941c155fe998 100644 --- a/llvm/test/CodeGen/AMDGPU/kernel-args.ll +++ b/llvm/test/CodeGen/AMDGPU/kernel-args.ll @@ -1,19 +1,19 @@ ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=SI,GCN,MESA-GCN,FUNC %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,MESA-VI,MESA-GCN,FUNC %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-code-object-v3 -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,HSA-VI,FUNC %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,HSA-GFX9,FUNC %s ; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=EG,EGCM,FUNC %s ; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=CM,EGCM,FUNC %s ; FUNC-LABEL: {{^}}i8_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c ; MESA-GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff -; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 -; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff +; HSA-GFX9: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 +; HSA-GFX9: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff ; EGCM: VTX_READ_8{{.*}} #3 @@ -25,13 +25,13 @@ define amdgpu_kernel void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) noun } ; FUNC-LABEL: {{^}}i8_zext_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c -; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 -; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff +; HSA-GFX9: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 +; HSA-GFX9: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff ; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, @@ -49,15 +49,15 @@ define amdgpu_kernel void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zero } ; FUNC-LABEL: {{^}}i8_sext_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c -; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 -; HSA-VI: s_sext_i32_i8 s{{[0-9]+}}, [[VAL]] -; HSA-VI: flat_store_dword +; HSA-GFX9: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 +; HSA-GFX9: s_sext_i32_i8 s{{[0-9]+}}, [[VAL]] +; HSA-GFX9: global_store_dword ; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, @@ -75,17 +75,17 @@ define amdgpu_kernel void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 sign } ; FUNC-LABEL: {{^}}i16_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c ; MESA-GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff -; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 -; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xffff{{$}} -; HSA-VI: flat_store_dword +; HSA-GFX9: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 +; HSA-GFX9: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xffff{{$}} +; HSA-GFX9: global_store_dword ; EGCM: VTX_READ_16 ; EGCM: KC0[2].Y @@ -96,15 +96,15 @@ define amdgpu_kernel void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) no } ; FUNC-LABEL: {{^}}i16_zext_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c -; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 -; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xffff{{$}} -; HSA-VI: flat_store_dword +; HSA-GFX9: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 +; HSA-GFX9: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xffff{{$}} +; HSA-GFX9: global_store_dword ; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, @@ -121,16 +121,16 @@ define amdgpu_kernel void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 ze } ; FUNC-LABEL: {{^}}i16_sext_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c -; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 -; HSA-VI: s_sext_i32_i16 s{{[0-9]+}}, [[VAL]] -; HSA-VI: flat_store_dword +; HSA-GFX9: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 +; HSA-GFX9: s_sext_i32_i16 s{{[0-9]+}}, [[VAL]] +; HSA-GFX9: global_store_dword ; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, @@ -147,13 +147,13 @@ define amdgpu_kernel void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 si } ; FUNC-LABEL: {{^}}i32_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM: T{{[0-9]\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c -; HSA-VI: s_load_dword s{{[0-9]}}, s[4:5], 0x8 +; HSA-GFX9: s_load_dword s{{[0-9]}}, s[4:5], 0x8 define amdgpu_kernel void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind { entry: store i32 %in, i32 addrspace(1)* %out, align 4 @@ -161,12 +161,12 @@ entry: } ; FUNC-LABEL: {{^}}f32_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM: T{{[0-9]\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0x8 define amdgpu_kernel void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind { entry: store float %in, float addrspace(1)* %out, align 4 @@ -174,8 +174,8 @@ entry: } ; FUNC-LABEL: {{^}}v2i8_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM: VTX_READ_8 ; EGCM: VTX_READ_8 @@ -189,15 +189,15 @@ entry: } ; FUNC-LABEL: {{^}}v2i16_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM: VTX_READ_16 ; EGCM: VTX_READ_16 ; SI: s_load_dword s{{[0-9]+}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c -; HSA-VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x8 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x8 define amdgpu_kernel void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) { entry: store <2 x i16> %in, <2 x i16> addrspace(1)* %out @@ -205,14 +205,14 @@ entry: } ; FUNC-LABEL: {{^}}v2i32_arg: -; HSA-VI: kernarg_segment_byte_size = 16 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 16 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W ; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb ; MESA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c -; HSA-VI: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x8 +; HSA-GFX9: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x8 define amdgpu_kernel void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind { entry: store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4 @@ -220,14 +220,14 @@ entry: } ; FUNC-LABEL: {{^}}v2f32_arg: -; HSA-VI: kernarg_segment_byte_size = 16 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 16 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W ; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb ; MESA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c -; HSA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[4:5], 0x8 +; HSA-GFX9: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[4:5], 0x8 define amdgpu_kernel void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind { entry: store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4 @@ -235,8 +235,8 @@ entry: } ; FUNC-LABEL: {{^}}v3i8_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40 ; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41 @@ -253,8 +253,8 @@ entry: } ; FUNC-LABEL: {{^}}v3i16_arg: -; HSA-VI: kernarg_segment_byte_size = 16 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 16 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44 ; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46 @@ -271,14 +271,14 @@ entry: } ; FUNC-LABEL: {{^}}v3i32_arg: -; HSA-VI: kernarg_segment_byte_size = 32 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 32 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34 -; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 +; HSA-GFX9: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 define amdgpu_kernel void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind { entry: store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4 @@ -286,14 +286,14 @@ entry: } ; FUNC-LABEL: {{^}}v3f32_arg: -; HSA-VI: kernarg_segment_byte_size = 32 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 32 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34 -; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 +; HSA-GFX9: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 define amdgpu_kernel void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind { entry: store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4 @@ -301,8 +301,8 @@ entry: } ; FUNC-LABEL: {{^}}v4i8_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM: VTX_READ_8 ; EGCM: VTX_READ_8 ; EGCM: VTX_READ_8 @@ -317,8 +317,8 @@ entry: } ; FUNC-LABEL: {{^}}v4i16_arg: -; HSA-VI: kernarg_segment_byte_size = 16 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 16 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM: VTX_READ_16 ; EGCM: VTX_READ_16 ; EGCM: VTX_READ_16 @@ -334,8 +334,8 @@ entry: ; MESA-VI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x24 ; MESA-VI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x2c -; HSA-VI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0 -; HSA-VI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 +; HSA-GFX9-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0 +; HSA-GFX9-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 define amdgpu_kernel void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) { entry: store <4 x i16> %in, <4 x i16> addrspace(1)* %out @@ -343,8 +343,8 @@ entry: } ; FUNC-LABEL: {{^}}v4i32_arg: -; HSA-VI: kernarg_segment_byte_size = 32 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 32 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W @@ -352,7 +352,7 @@ entry: ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34 -; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 +; HSA-GFX9: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 define amdgpu_kernel void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind { entry: store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4 @@ -360,15 +360,15 @@ entry: } ; FUNC-LABEL: {{^}}v4f32_arg: -; HSA-VI: kernarg_segment_byte_size = 32 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 32 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34 -; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 +; HSA-GFX9: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 define amdgpu_kernel void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind { entry: store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4 @@ -377,8 +377,8 @@ entry: ; FIXME: Lots of unpack and re-pack junk on VI ; FUNC-LABEL: {{^}}v8i8_arg: -; HSA-VI: kernarg_segment_byte_size = 16 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 16 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM: VTX_READ_8 ; EGCM: VTX_READ_8 ; EGCM: VTX_READ_8 @@ -405,8 +405,8 @@ entry: } ; FUNC-LABEL: {{^}}v8i16_arg: -; HSA-VI: kernarg_segment_byte_size = 32 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 32 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM: VTX_READ_16 ; EGCM: VTX_READ_16 ; EGCM: VTX_READ_16 @@ -423,7 +423,7 @@ entry: ; MESA-VI: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x34 -; HSA-VI: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x10 +; HSA-GFX9: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x10 define amdgpu_kernel void @v8i16_arg(<8 x i16> addrspace(1)* %out, <8 x i16> %in) { entry: store <8 x i16> %in, <8 x i16> addrspace(1)* %out @@ -431,8 +431,8 @@ entry: } ; FUNC-LABEL: {{^}}v8i32_arg: -; HSA-VI: kernarg_segment_byte_size = 64 -; HSA-VI: kernarg_segment_alignment = 5 +; HSA-GFX9: kernarg_segment_byte_size = 64 +; HSA-GFX9: kernarg_segment_alignment = 5 ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W @@ -444,7 +444,7 @@ entry: ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11 ; MESA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44 -; HSA-VI: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x20 +; HSA-GFX9: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x20 define amdgpu_kernel void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind { entry: store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4 @@ -452,8 +452,8 @@ entry: } ; FUNC-LABEL: {{^}}v8f32_arg: -; HSA-VI: kernarg_segment_byte_size = 64 -; HSA-VI: kernarg_segment_alignment = 5 +; HSA-GFX9: kernarg_segment_byte_size = 64 +; HSA-GFX9: kernarg_segment_alignment = 5 ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W @@ -472,8 +472,8 @@ entry: ; FIXME: Pack/repack on VI ; FUNC-LABEL: {{^}}v16i8_arg: -; HSA-VI: kernarg_segment_byte_size = 32 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 32 +; HSA-GFX9: kernarg_segment_alignment = 4 ; EGCM: VTX_READ_8 ; EGCM: VTX_READ_8 ; EGCM: VTX_READ_8 @@ -508,8 +508,8 @@ entry: } ; FUNC-LABEL: {{^}}v16i16_arg: -; HSA-VI: kernarg_segment_byte_size = 64 -; HSA-VI: kernarg_segment_alignment = 5 +; HSA-GFX9: kernarg_segment_byte_size = 64 +; HSA-GFX9: kernarg_segment_alignment = 5 ; EGCM: VTX_READ_16 ; EGCM: VTX_READ_16 ; EGCM: VTX_READ_16 @@ -535,7 +535,7 @@ entry: ; MESA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44 -; HSA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20 +; HSA-GFX9: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20 define amdgpu_kernel void @v16i16_arg(<16 x i16> addrspace(1)* %out, <16 x i16> %in) { entry: store <16 x i16> %in, <16 x i16> addrspace(1)* %out @@ -543,8 +543,8 @@ entry: } ; FUNC-LABEL: {{^}}v16i32_arg: -; HSA-VI: kernarg_segment_byte_size = 128 -; HSA-VI: kernarg_segment_alignment = 6 +; HSA-GFX9: kernarg_segment_byte_size = 128 +; HSA-GFX9: kernarg_segment_alignment = 6 ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W @@ -563,7 +563,7 @@ entry: ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X ; SI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x19 ; MESA-VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64 -; HSA-VI: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40 +; HSA-GFX9: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40 define amdgpu_kernel void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind { entry: store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4 @@ -571,8 +571,8 @@ entry: } ; FUNC-LABEL: {{^}}v16f32_arg: -; HSA-VI: kernarg_segment_byte_size = 128 -; HSA-VI: kernarg_segment_alignment = 6 +; HSA-GFX9: kernarg_segment_byte_size = 128 +; HSA-GFX9: kernarg_segment_alignment = 6 ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W @@ -591,7 +591,7 @@ entry: ; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X ; SI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x19 ; MESA-VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64 -; HSA-VI: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40 +; HSA-GFX9: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40 define amdgpu_kernel void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind { entry: store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4 @@ -600,7 +600,7 @@ entry: ; FUNC-LABEL: {{^}}kernel_arg_i64: ; MESA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[0:1], 0x24 -; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 +; HSA-GFX9: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 ; MESA-GCN: buffer_store_dwordx2 define amdgpu_kernel void @kernel_arg_i64(i64 addrspace(1)* %out, i64 %a) nounwind { @@ -613,7 +613,7 @@ define amdgpu_kernel void @kernel_arg_i64(i64 addrspace(1)* %out, i64 %a) nounwi ; MESA-VI-DAG: s_load_dwordx4 s[{{[0-9]:[0-9]}}], s[0:1], 0x24 ; MESA-GCN: buffer_store_dwordx2 -; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 +; HSA-GFX9: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 define amdgpu_kernel void @f64_kernel_arg(double addrspace(1)* %out, double %in) { entry: store double %in, double addrspace(1)* %out @@ -630,10 +630,10 @@ entry: ; } ; FUNC-LABEL: {{^}}i65_arg: -; HSA-VI: kernarg_segment_byte_size = 24 -; HSA-VI: kernarg_segment_alignment = 4 -; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0 -; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 +; HSA-GFX9: kernarg_segment_byte_size = 24 +; HSA-GFX9: kernarg_segment_alignment = 4 +; HSA-GFX9: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0 +; HSA-GFX9: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 define amdgpu_kernel void @i65_arg(i65 addrspace(1)* nocapture %out, i65 %in) nounwind { entry: store i65 %in, i65 addrspace(1)* %out, align 4 @@ -641,20 +641,20 @@ entry: } ; FUNC-LABEL: {{^}}i1_arg: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; GCN: s_load_dword s ; GCN: s_and_b32 -; GCN: {{buffer|flat}}_store_byte +; GCN: {{buffer|flat|global}}_store_byte define amdgpu_kernel void @i1_arg(i1 addrspace(1)* %out, i1 %x) nounwind { store i1 %x, i1 addrspace(1)* %out, align 1 ret void } ; FUNC-LABEL: {{^}}i1_arg_zext_i32: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; GCN: s_load_dword ; SGCN: buffer_store_dword @@ -665,11 +665,11 @@ define amdgpu_kernel void @i1_arg_zext_i32(i32 addrspace(1)* %out, i1 %x) nounwi } ; FUNC-LABEL: {{^}}i1_arg_zext_i64: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; GCN: s_load_dword s -; GCN: {{buffer|flat}}_store_dwordx2 +; GCN: {{buffer|flat|global}}_store_dwordx2 define amdgpu_kernel void @i1_arg_zext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { %ext = zext i1 %x to i64 store i64 %ext, i64 addrspace(1)* %out, align 8 @@ -677,11 +677,11 @@ define amdgpu_kernel void @i1_arg_zext_i64(i64 addrspace(1)* %out, i1 %x) nounwi } ; FUNC-LABEL: {{^}}i1_arg_sext_i32: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; GCN: s_load_dword -; GCN: {{buffer|flat}}_store_dword +; GCN: {{buffer|flat|global}}_store_dword define amdgpu_kernel void @i1_arg_sext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { %ext = sext i1 %x to i32 store i32 %ext, i32addrspace(1)* %out, align 4 @@ -689,12 +689,12 @@ define amdgpu_kernel void @i1_arg_sext_i32(i32 addrspace(1)* %out, i1 %x) nounwi } ; FUNC-LABEL: {{^}}i1_arg_sext_i64: -; HSA-VI: kernarg_segment_byte_size = 12 -; HSA-VI: kernarg_segment_alignment = 4 +; HSA-GFX9: kernarg_segment_byte_size = 12 +; HSA-GFX9: kernarg_segment_alignment = 4 ; GCN: s_load_dword ; GCN: s_bfe_i64 -; GCN: {{buffer|flat}}_store_dwordx2 +; GCN: {{buffer|flat|global}}_store_dwordx2 define amdgpu_kernel void @i1_arg_sext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { %ext = sext i1 %x to i64 store i64 %ext, i64 addrspace(1)* %out, align 8 @@ -702,7 +702,7 @@ define amdgpu_kernel void @i1_arg_sext_i64(i64 addrspace(1)* %out, i1 %x) nounwi } ; FUNC-LABEL: {{^}}empty_struct_arg: -; HSA-VI: kernarg_segment_byte_size = 0 +; HSA-GFX9: kernarg_segment_byte_size = 0 define amdgpu_kernel void @empty_struct_arg({} %in) nounwind { ret void } @@ -718,11 +718,11 @@ define amdgpu_kernel void @empty_struct_arg({} %in) nounwind { ; FIXME: Total argument size is computed wrong ; FUNC-LABEL: {{^}}struct_argument_alignment: -; HSA-VI: kernarg_segment_byte_size = 40 -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 -; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x18 -; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20 +; HSA-GFX9: kernarg_segment_byte_size = 40 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 +; HSA-GFX9: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0x18 +; HSA-GFX9: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20 define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32, i64} %arg1) { %val0 = extractvalue {i32, i64} %arg0, 0 %val1 = extractvalue {i32, i64} %arg0, 1 @@ -738,11 +738,11 @@ define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32, ; No padding between i8 and next struct, but round up at end to 4 byte ; multiple. ; FUNC-LABEL: {{^}}packed_struct_argument_alignment: -; HSA-VI: kernarg_segment_byte_size = 28 -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 -; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x4 -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0xc -; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x10 +; HSA-GFX9: kernarg_segment_byte_size = 28 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 +; HSA-GFX9: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x4 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0xc +; HSA-GFX9: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x10 define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0, i8, <{i32, i64}> %arg1) { %val0 = extractvalue <{i32, i64}> %arg0, 0 %val1 = extractvalue <{i32, i64}> %arg0, 1 @@ -756,12 +756,12 @@ define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0, } ; GCN-LABEL: {{^}}struct_argument_alignment_after: -; HSA-VI: kernarg_segment_byte_size = 64 -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 -; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x18 -; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20 -; HSA-VI: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x30 +; HSA-GFX9: kernarg_segment_byte_size = 64 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 +; HSA-GFX9: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0x18 +; HSA-GFX9: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20 +; HSA-GFX9: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x30 define amdgpu_kernel void @struct_argument_alignment_after({i32, i64} %arg0, i8, {i32, i64} %arg2, i8, <4 x i32> %arg4) { %val0 = extractvalue {i32, i64} %arg0, 0 %val1 = extractvalue {i32, i64} %arg0, 1 @@ -776,10 +776,10 @@ define amdgpu_kernel void @struct_argument_alignment_after({i32, i64} %arg0, i8, } ; GCN-LABEL: {{^}}array_3xi32: -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x4 -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8 -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0xc +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0x4 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0x8 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0xc define amdgpu_kernel void @array_3xi32(i16 %arg0, [3 x i32] %arg1) { store volatile i16 %arg0, i16 addrspace(1)* undef store volatile [3 x i32] %arg1, [3 x i32] addrspace(1)* undef @@ -788,11 +788,9 @@ define amdgpu_kernel void @array_3xi32(i16 %arg0, [3 x i32] %arg1) { ; FIXME: Why not all scalar loads? ; GCN-LABEL: {{^}}array_3xi16: -; HSA-VI: s_add_u32 s{{[0-9]+}}, s4, 2 -; HSA-VI: s_addc_u32 s{{[0-9]+}}, s5, 0 -; HSA-VI: flat_load_ushort -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 -; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x4 +; HSA-GFX9: global_load_ushort v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:2 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 +; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0x4 define amdgpu_kernel void @array_3xi16(i8 %arg0, [3 x i16] %arg1) { store volatile i8 %arg0, i8 addrspace(1)* undef store volatile [3 x i16] %arg1, [3 x i16] addrspace(1)* undef