From faad6205696fa07ef9a51bfc1f8e667a6d9005cd Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Sat, 21 Mar 2015 04:04:50 +0000 Subject: [PATCH] Remove the bare getSubtargetImpl call from the AArch64 port. As part of this add a test that shows we can generate code for functions that specifically enable a subtarget feature. llvm-svn: 232884 --- .../Target/AArch64/AArch64TargetMachine.cpp | 1 - .../lib/Target/AArch64/AArch64TargetMachine.h | 5 --- .../AArch64/function-subtarget-features.ll | 37 +++++++++++++++++++ 3 files changed, 37 insertions(+), 6 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/function-subtarget-features.ll diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index ed948cb9d269..187d2ce2088e 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -127,7 +127,6 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT, : LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS, Options, RM, CM, OL), TLOF(createTLOF(Triple(getTargetTriple()))), - Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) { initAsmInfo(); } diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h index e73aa877db7d..ec34fad97c8d 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h @@ -24,7 +24,6 @@ namespace llvm { class AArch64TargetMachine : public LLVMTargetMachine { protected: std::unique_ptr TLOF; - AArch64Subtarget Subtarget; mutable StringMap> SubtargetMap; public: @@ -34,10 +33,6 @@ public: CodeGenOpt::Level OL, bool IsLittleEndian); ~AArch64TargetMachine() override; - - const AArch64Subtarget *getSubtargetImpl() const override { - return &Subtarget; - } const AArch64Subtarget *getSubtargetImpl(const Function &F) const override; // Pass Pipeline Configuration diff --git a/llvm/test/CodeGen/AArch64/function-subtarget-features.ll b/llvm/test/CodeGen/AArch64/function-subtarget-features.ll new file mode 100644 index 000000000000..933cb87b7432 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/function-subtarget-features.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-gnu" + +; This test verifies that we can enable subtarget features via +; the function attributes and generate appropriate code (or, +; in this case, select the instruction at all). + +; Function Attrs: nounwind +define <16 x i8> @foo(<16 x i8> %data, <16 x i8> %key) #0 { +entry: + %__p0.addr.i = alloca <16 x i8>, align 16 + %__p1.addr.i = alloca <16 x i8>, align 16 + %__ret.i = alloca <16 x i8>, align 16 + %data.addr = alloca <16 x i8>, align 16 + %key.addr = alloca <16 x i8>, align 16 + store <16 x i8> %data, <16 x i8>* %data.addr, align 16 + store <16 x i8> %key, <16 x i8>* %key.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %data.addr, align 16 + %1 = load <16 x i8>, <16 x i8>* %key.addr, align 16 + store <16 x i8> %0, <16 x i8>* %__p0.addr.i, align 16 + store <16 x i8> %1, <16 x i8>* %__p1.addr.i, align 16 + %2 = load <16 x i8>, <16 x i8>* %__p0.addr.i, align 16 + %3 = load <16 x i8>, <16 x i8>* %__p1.addr.i, align 16 + %vaeseq_v.i = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %2, <16 x i8> %3) + store <16 x i8> %vaeseq_v.i, <16 x i8>* %__ret.i, align 16 + %4 = load <16 x i8>, <16 x i8>* %__ret.i, align 16 + ret <16 x i8> %4 +} + +; CHECK: foo +; CHECK: aese + +; Function Attrs: nounwind readnone +declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8>, <16 x i8>) + +attributes #0 = { nounwind "target-features"="+neon,+crc,+crypto" }