forked from OSchip/llvm-project
[mips] Prevent %lo relocation being used on MSA loads and stores.
Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 llvm-svn: 202717
This commit is contained in:
Daniel Sanders
parent
2a710d0a5b
commit
fa961d76f0
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@ -93,6 +93,12 @@ bool MipsDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
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SDValue &Offset, SDValue &Alias) {
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llvm_unreachable("Unimplemented function.");
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@ -73,6 +73,10 @@ private:
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virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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/// Match addr+simm10 and addr
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virtual bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
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SDValue &Offset, SDValue &Alias);
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@ -247,6 +247,8 @@ def calltarget : Operand<iPTR> {
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let EncoderMethod = "getJumpTargetOpValue";
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}
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def simm10 : Operand<i32>;
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def simm16 : Operand<i32> {
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let DecoderMethod= "DecodeSimm16";
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}
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@ -314,6 +316,7 @@ def mem : mem_generic;
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// MSA specific address operand
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def mem_msa : mem_generic {
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let MIOperandInfo = (ops ptr_rc, simm10);
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let EncoderMethod = "getMSAMemEncoding";
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}
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@ -406,6 +409,8 @@ def addrRegReg :
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def addrDefault :
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ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
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def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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@ -94,8 +94,6 @@ def uimm8 : Operand<i32> {
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def simm5 : Operand<i32>;
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def simm10 : Operand<i32>;
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def vsplat_uimm1 : Operand<vAny> {
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let PrintMethod = "printUnsignedImm8";
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}
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@ -2292,7 +2290,7 @@ class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d,
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class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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ValueType TyNode, RegisterOperand ROWD,
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Operand MemOpnd = mem_msa, ComplexPattern Addr = addrRegImm,
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Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs ROWD:$wd);
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dag InOperandList = (ins MemOpnd:$addr);
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@ -2622,7 +2620,7 @@ class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d,
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class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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ValueType TyNode, RegisterOperand ROWD,
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Operand MemOpnd = mem_msa, ComplexPattern Addr = addrRegImm,
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Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
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@ -3494,39 +3492,16 @@ class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
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def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
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(COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
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def : MSAPat<(v16i8 (load addr:$addr)), (LD_B addr:$addr)>;
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def : MSAPat<(v8i16 (load addr:$addr)), (LD_H addr:$addr)>;
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def : MSAPat<(v4i32 (load addr:$addr)), (LD_W addr:$addr)>;
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def : MSAPat<(v2i64 (load addr:$addr)), (LD_D addr:$addr)>;
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def : MSAPat<(v8f16 (load addr:$addr)), (LD_H addr:$addr)>;
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def : MSAPat<(v4f32 (load addr:$addr)), (LD_W addr:$addr)>;
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def : MSAPat<(v2f64 (load addr:$addr)), (LD_D addr:$addr)>;
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def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>;
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def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>;
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def : MSAPat<(v2f64 (load addrimm10:$addr)), (LD_D addrimm10:$addr)>;
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def : MSAPat<(v8f16 (load addrRegImm:$addr)), (LD_H addrRegImm:$addr)>;
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def : MSAPat<(v4f32 (load addrRegImm:$addr)), (LD_W addrRegImm:$addr)>;
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def : MSAPat<(v2f64 (load addrRegImm:$addr)), (LD_D addrRegImm:$addr)>;
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def : MSAPat<(store (v16i8 MSA128B:$ws), addr:$addr),
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(ST_B MSA128B:$ws, addr:$addr)>;
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def : MSAPat<(store (v8i16 MSA128H:$ws), addr:$addr),
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(ST_H MSA128H:$ws, addr:$addr)>;
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def : MSAPat<(store (v4i32 MSA128W:$ws), addr:$addr),
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(ST_W MSA128W:$ws, addr:$addr)>;
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def : MSAPat<(store (v2i64 MSA128D:$ws), addr:$addr),
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(ST_D MSA128D:$ws, addr:$addr)>;
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def : MSAPat<(store (v8f16 MSA128H:$ws), addr:$addr),
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(ST_H MSA128H:$ws, addr:$addr)>;
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def : MSAPat<(store (v4f32 MSA128W:$ws), addr:$addr),
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(ST_W MSA128W:$ws, addr:$addr)>;
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def : MSAPat<(store (v2f64 MSA128D:$ws), addr:$addr),
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(ST_D MSA128D:$ws, addr:$addr)>;
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def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrRegImm:$addr),
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(ST_H MSA128H:$ws, addrRegImm:$addr)>;
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def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrRegImm:$addr),
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(ST_W MSA128W:$ws, addrRegImm:$addr)>;
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def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrRegImm:$addr),
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(ST_D MSA128D:$ws, addrRegImm:$addr)>;
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def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr),
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(ST_H MSA128H:$ws, addrimm10:$addr)>;
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def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10:$addr),
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(ST_W MSA128W:$ws, addrimm10:$addr)>;
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def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10:$addr),
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(ST_D MSA128D:$ws, addrimm10:$addr)>;
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class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
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RegisterOperand ROWS = ROWD,
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@ -248,18 +248,49 @@ SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
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SDValue(AddCarry, 0));
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}
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/// ComplexPattern used on MipsInstrInfo
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/// Used on Mips Load/Store instructions
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bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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EVT ValTy = Addr.getValueType();
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// if Address is FI, get the TargetFrameIndex.
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/// Match frameindex
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bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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EVT ValTy = Addr.getValueType();
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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Offset = CurDAG->getTargetConstant(0, ValTy);
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return true;
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}
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return false;
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}
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/// Match frameindex+offset and frameindex|offset
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bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
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SDValue &Offset,
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unsigned OffsetBits) const {
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isIntN(OffsetBits, CN->getSExtValue())) {
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EVT ValTy = Addr.getValueType();
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0)))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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else
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
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return true;
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}
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}
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return false;
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}
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/// ComplexPattern used on MipsInstrInfo
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/// Used on Mips Load/Store instructions
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bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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// if Address is FI, get the TargetFrameIndex.
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if (selectAddrFrameIndex(Addr, Base, Offset))
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return true;
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// on PIC code Load GA
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if (Addr.getOpcode() == MipsISD::Wrapper) {
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@ -275,21 +306,8 @@ bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
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}
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// Addresses of the form FI+const or FI|const
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isInt<16>(CN->getSExtValue())) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0)))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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else
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
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return true;
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}
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}
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if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
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return true;
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// Operand is a result from an ADD.
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if (Addr.getOpcode() == ISD::ADD) {
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@ -343,27 +361,25 @@ bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
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selectAddrDefault(Addr, Base, Offset);
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}
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bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (selectAddrFrameIndex(Addr, Base, Offset))
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return true;
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if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
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return true;
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return false;
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}
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/// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
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bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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EVT ValTy = Addr.getValueType();
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if (selectAddrFrameIndex(Addr, Base, Offset))
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return true;
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// Addresses of the form FI+const or FI|const
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isInt<12>(CN->getSExtValue())) {
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// If the first operand is a FI then get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0)))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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else
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
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return true;
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}
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}
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if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
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return true;
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return false;
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}
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@ -374,6 +390,17 @@ bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
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selectAddrDefault(Addr, Base, Offset);
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}
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bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (selectAddrRegImm10(Addr, Base, Offset))
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return true;
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if (selectAddrDefault(Addr, Base, Offset))
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return true;
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return false;
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}
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// Select constant vector splats.
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//
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// Returns true and sets Imm if:
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@ -40,6 +40,10 @@ private:
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SDNode *selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS,
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SDLoc DL, SDNode *Node) const;
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bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
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bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
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unsigned OffsetBits) const;
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virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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@ -52,12 +56,18 @@ private:
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virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectAddrRegImm10(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectAddrRegImm12(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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/// \brief Select constant vector splats.
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virtual bool selectVSplat(SDNode *N, APInt &Imm) const;
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/// \brief Select constant vector splats whose value fits in a given integer.
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@ -295,7 +295,8 @@ define void @fexp2_v2f64_2(<2 x double>* %c, <2 x double>* %a) nounwind {
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1)
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%3 = fmul <2 x double> <double 2.0, double 2.0>, %2
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; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo(
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; CHECK-DAG: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[G_PTR]])
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; CHECK-DAG: fexp2.d [[R4:\$w[0-9]+]], [[R3]], [[R1]]
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store <2 x double> %3, <2 x double>* %c
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; CHECK-DAG: st.d [[R4]], 0($4)
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@ -18,10 +18,12 @@ define void @const_v16i8() nounwind {
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; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 1
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store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 31>, <16 x i8>*@v16i8
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; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], %lo(
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; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
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store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8
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; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], %lo(
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; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
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store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8
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; MIPS32-BE: ldi.h [[R1:\$w[0-9]+]], 256
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@ -35,7 +37,8 @@ define void @const_v16i8() nounwind {
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; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
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store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8
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; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], %lo(
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; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
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ret void
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; MIPS32-AE: .size const_v16i8
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@ -51,7 +54,8 @@ define void @const_v8i16() nounwind {
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; MIPS32-AE: ldi.h [[R1:\$w[0-9]+]], 1
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store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 2, i16 1, i16 1, i16 1, i16 31>, <8 x i16>*@v8i16
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; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], %lo(
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; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]])
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store volatile <8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>, <8 x i16>*@v8i16
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; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 4
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|
|
@ -64,7 +68,8 @@ define void @const_v8i16() nounwind {
|
|||
; MIPS32-AE-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
|
||||
|
||||
store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16
|
||||
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
ret void
|
||||
; MIPS32-AE: .size const_v8i16
|
||||
|
|
@ -80,7 +85,8 @@ define void @const_v4i32() nounwind {
|
|||
; MIPS32-AE: ldi.w [[R1:\$w[0-9]+]], 1
|
||||
|
||||
store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 31>, <4 x i32>*@v4i32
|
||||
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
store volatile <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009>, <4 x i32>*@v4i32
|
||||
; MIPS32-AE: ldi.b [[R1:\$w[0-9]+]], 1
|
||||
|
|
@ -89,10 +95,12 @@ define void @const_v4i32() nounwind {
|
|||
; MIPS32-AE: ldi.h [[R1:\$w[0-9]+]], 1
|
||||
|
||||
store volatile <4 x i32> <i32 1, i32 2, i32 1, i32 2>, <4 x i32>*@v4i32
|
||||
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32
|
||||
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
ret void
|
||||
; MIPS32-AE: .size const_v4i32
|
||||
|
|
@ -117,10 +125,12 @@ define void @const_v2i64() nounwind {
|
|||
; MIPS32-AE: ldi.d [[R1:\$w[0-9]+]], 1
|
||||
|
||||
store volatile <2 x i64> <i64 1, i64 31>, <2 x i64>*@v2i64
|
||||
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64
|
||||
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32-AE: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
ret void
|
||||
; MIPS32-AE: .size const_v2i64
|
||||
|
|
|
|||
|
|
@ -17,7 +17,8 @@ define void @const_v4f32() nounwind {
|
|||
; MIPS32: fill.w [[R2:\$w[0-9]+]], [[R1]]
|
||||
|
||||
store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
|
||||
; MIPS32: lui [[R1:\$[0-9]+]], 18304
|
||||
|
|
@ -25,10 +26,12 @@ define void @const_v4f32() nounwind {
|
|||
; MIPS32: fill.w [[R3:\$w[0-9]+]], [[R2]]
|
||||
|
||||
store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
ret void
|
||||
; MIPS32: .size const_v4f32
|
||||
|
|
@ -41,22 +44,28 @@ define void @const_v2f64() nounwind {
|
|||
; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
|
||||
|
||||
store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
|
||||
|
||||
ret void
|
||||
; MIPS32: .size const_v2f64
|
||||
|
|
|
|||
|
|
@ -37,7 +37,8 @@ define void @lshr_v4i32(<4 x i32>* %c) nounwind {
|
|||
%2 = lshr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>,
|
||||
<i32 0, i32 1, i32 2, i32 3>
|
||||
; CHECK-NOT: srl
|
||||
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], %lo
|
||||
; CHECK-DAG: addiu [[CPOOL:\$[0-9]+]], {{.*}}, %lo($
|
||||
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0([[CPOOL]])
|
||||
; CHECK-NOT: srl
|
||||
store volatile <4 x i32> %2, <4 x i32>* %c
|
||||
; CHECK-DAG: st.w [[R1]], 0($4)
|
||||
|
|
|
|||
|
|
@ -7,7 +7,8 @@ define void @vshf_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
|
|||
%1 = load <16 x i8>* %a
|
||||
; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
|
||||
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
|
||||
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], %lo
|
||||
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
|
||||
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[PTR_A]])
|
||||
; CHECK-DAG: vshf.b [[R3]], [[R1]], [[R1]]
|
||||
store <16 x i8> %2, <16 x i8>* %c
|
||||
; CHECK-DAG: st.b [[R3]], 0($4)
|
||||
|
|
@ -37,7 +38,8 @@ define void @vshf_v16i8_2(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
|
|||
%2 = load <16 x i8>* %b
|
||||
; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
|
||||
%3 = shufflevector <16 x i8> %1, <16 x i8> %2, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 16>
|
||||
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], %lo
|
||||
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
|
||||
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[PTR_A]])
|
||||
; CHECK-DAG: vshf.b [[R3]], [[R2]], [[R2]]
|
||||
store <16 x i8> %3, <16 x i8>* %c
|
||||
; CHECK-DAG: st.b [[R3]], 0($4)
|
||||
|
|
@ -54,7 +56,8 @@ define void @vshf_v16i8_3(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind
|
|||
%2 = load <16 x i8>* %b
|
||||
; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
|
||||
%3 = shufflevector <16 x i8> %1, <16 x i8> %2, <16 x i32> <i32 17, i32 24, i32 25, i32 18, i32 19, i32 20, i32 28, i32 19, i32 1, i32 8, i32 9, i32 2, i32 3, i32 4, i32 12, i32 3>
|
||||
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], %lo
|
||||
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
|
||||
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[PTR_A]])
|
||||
; CHECK-DAG: vshf.b [[R3]], [[R1]], [[R2]]
|
||||
store <16 x i8> %3, <16 x i8>* %c
|
||||
; CHECK-DAG: st.b [[R3]], 0($4)
|
||||
|
|
@ -83,7 +86,8 @@ define void @vshf_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
|
|||
%1 = load <8 x i16>* %a
|
||||
; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
|
||||
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
|
||||
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], %lo
|
||||
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
|
||||
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[PTR_A]])
|
||||
; CHECK-DAG: vshf.h [[R3]], [[R1]], [[R1]]
|
||||
store <8 x i16> %2, <8 x i16>* %c
|
||||
; CHECK-DAG: st.h [[R3]], 0($4)
|
||||
|
|
@ -113,7 +117,8 @@ define void @vshf_v8i16_2(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
|
|||
%2 = load <8 x i16>* %b
|
||||
; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
|
||||
%3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
|
||||
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], %lo
|
||||
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
|
||||
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[PTR_A]])
|
||||
; CHECK-DAG: vshf.h [[R3]], [[R2]], [[R2]]
|
||||
store <8 x i16> %3, <8 x i16>* %c
|
||||
; CHECK-DAG: st.h [[R3]], 0($4)
|
||||
|
|
@ -130,7 +135,8 @@ define void @vshf_v8i16_3(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind
|
|||
%2 = load <8 x i16>* %b
|
||||
; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
|
||||
%3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 1, i32 8, i32 9, i32 2, i32 3, i32 4, i32 12, i32 3>
|
||||
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], %lo
|
||||
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
|
||||
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[PTR_A]])
|
||||
; CHECK-DAG: vshf.h [[R3]], [[R1]], [[R2]]
|
||||
store <8 x i16> %3, <8 x i16>* %c
|
||||
; CHECK-DAG: st.h [[R3]], 0($4)
|
||||
|
|
@ -207,7 +213,8 @@ define void @vshf_v4i32_3(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind
|
|||
%2 = load <4 x i32>* %b
|
||||
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
|
||||
%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 1, i32 5, i32 6, i32 4>
|
||||
; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], %lo
|
||||
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
|
||||
; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[PTR_A]])
|
||||
; CHECK-DAG: vshf.w [[R3]], [[R1]], [[R2]]
|
||||
store <4 x i32> %3, <4 x i32>* %c
|
||||
; CHECK-DAG: st.w [[R3]], 0($4)
|
||||
|
|
@ -236,7 +243,8 @@ define void @vshf_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
|
|||
%1 = load <2 x i64>* %a
|
||||
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
|
||||
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
|
||||
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo
|
||||
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
|
||||
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[PTR_A]])
|
||||
; CHECK-DAG: vshf.d [[R3]], [[R1]], [[R1]]
|
||||
store <2 x i64> %2, <2 x i64>* %c
|
||||
; CHECK-DAG: st.d [[R3]], 0($4)
|
||||
|
|
@ -266,7 +274,8 @@ define void @vshf_v2i64_2(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
|
|||
%2 = load <2 x i64>* %b
|
||||
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
|
||||
%3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 3, i32 2>
|
||||
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo
|
||||
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
|
||||
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[PTR_A]])
|
||||
; CHECK-DAG: vshf.d [[R3]], [[R2]], [[R2]]
|
||||
store <2 x i64> %3, <2 x i64>* %c
|
||||
; CHECK-DAG: st.d [[R3]], 0($4)
|
||||
|
|
@ -283,7 +292,8 @@ define void @vshf_v2i64_3(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
|
|||
%2 = load <2 x i64>* %b
|
||||
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
|
||||
%3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 1, i32 2>
|
||||
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo
|
||||
; CHECK-DAG: addiu [[PTR_A:\$[0-9]+]], {{.*}}, %lo($
|
||||
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[PTR_A]])
|
||||
; CHECK-DAG: vshf.d [[R3]], [[R1]], [[R2]]
|
||||
store <2 x i64> %3, <2 x i64>* %c
|
||||
; CHECK-DAG: st.d [[R3]], 0($4)
|
||||
|
|
|
|||
Loading…
Reference in New Issue