maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[Hexagon] Deleting versions of compare-not that don't have encoding information. Updating references. 

llvm-svn: 226003
This commit is contained in:
Colin LeMahieu 2015-01-14 16:49:12 +00:00
parent 1ed2bb592a
commit fa947906bf
3 changed files with 9 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
View File

@ -553,7 +553,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,
Cmp = !Negated ? Comparison::GTs : Comparison::LEs; Cmp = !Negated ? Comparison::GTs : Comparison::LEs;
break; break;
// Very limited support for byte/halfword compares. // Very limited support for byte/halfword compares.
case Hexagon::CMPbEQri_V4: case Hexagon::A4_cmpbeqi:
case Hexagon::CMPhEQri_V4: { case Hexagon::CMPhEQri_V4: {
if (IVBump != 1) if (IVBump != 1)
return nullptr; return nullptr;
@ -574,7 +574,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,
} }
if (InitV >= EndV) if (InitV >= EndV)
return nullptr; return nullptr;
if (CondOpc == Hexagon::CMPbEQri_V4) { if (CondOpc == Hexagon::A4_cmpbeqi) {
if (!isInt<8>(InitV) || !isInt<8>(EndV)) if (!isInt<8>(InitV) || !isInt<8>(EndV))
return nullptr; return nullptr;
} else { // Hexagon::CMPhEQri_V4 } else { // Hexagon::CMPhEQri_V4

4
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -358,7 +358,7 @@ bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
SrcReg = MI->getOperand(1).getReg(); SrcReg = MI->getOperand(1).getReg();
Mask = ~0; Mask = ~0;
break; break;
case Hexagon::CMPbEQri_V4: case Hexagon::A4_cmpbeqi:
case Hexagon::CMPbEQrr_sbsb_V4: case Hexagon::CMPbEQrr_sbsb_V4:
case Hexagon::CMPbEQrr_ubub_V4: case Hexagon::CMPbEQrr_ubub_V4:
case Hexagon::CMPbGTUri_V4: case Hexagon::CMPbGTUri_V4:
@ -400,7 +400,7 @@ bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
case Hexagon::C2_cmpeqi: case Hexagon::C2_cmpeqi:
case Hexagon::C2_cmpgtui: case Hexagon::C2_cmpgtui:
case Hexagon::C2_cmpgti: case Hexagon::C2_cmpgti:
case Hexagon::CMPbEQri_V4: case Hexagon::A4_cmpbeqi:
case Hexagon::CMPbGTUri_V4: case Hexagon::CMPbGTUri_V4:
case Hexagon::CMPhEQri_V4: case Hexagon::CMPhEQri_V4:
case Hexagon::CMPhGTUri_V4: case Hexagon::CMPhGTUri_V4:

46
llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -146,6 +146,8 @@ class CmpInReg<PatFrag Op>
def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>; def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>; def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
def: T_cmp32_rr_pat<C4_cmpneq, setne, i1>;
class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm> class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
"$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>, "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
@ -2710,47 +2712,9 @@ let opExtentBits = 9 in
def C4_cmplteui : CMP_NOT_REG_IMM <"gtu", 0b10, u9Ext, [(set (i1 PredRegs:$dst), def C4_cmplteui : CMP_NOT_REG_IMM <"gtu", 0b10, u9Ext, [(set (i1 PredRegs:$dst),
(not (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)))]>; (not (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)))]>;
// p=!cmp.eq(r1,r2)
let isCompare = 1, validSubTargets = HasV4SubT in
def CMPnotEQ_rr : ALU32_rr<(outs PredRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = !cmp.eq($src1, $src2)",
[(set (i1 PredRegs:$dst),
(setne (i32 IntRegs:$src1), (i32 IntRegs:$src2)))]>,
Requires<[HasV4T]>;
// p=!cmp.gt(r1,r2)
let isCompare = 1, validSubTargets = HasV4SubT in
def CMPnotGT_rr : ALU32_rr<(outs PredRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = !cmp.gt($src1, $src2)",
[(set (i1 PredRegs:$dst),
(not (setgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
Requires<[HasV4T]>;
// p=!cmp.gtu(r1,r2)
let isCompare = 1, validSubTargets = HasV4SubT in
def CMPnotGTU_rr : ALU32_rr<(outs PredRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = !cmp.gtu($src1, $src2)",
[(set (i1 PredRegs:$dst),
(not (setugt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
Requires<[HasV4T]>;
let isCompare = 1, validSubTargets = HasV4SubT in
def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
(ins IntRegs:$src1, u8Imm:$src2),
"$dst = cmpb.eq($src1, #$src2)",
[(set (i1 PredRegs:$dst),
(seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
Requires<[HasV4T]>;
def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)), def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
bb:$offset), bb:$offset),
(J2_jumpf (CMPbEQri_V4 (i32 IntRegs:$src1), u8ImmPred:$src2), (J2_jumpf (A4_cmpbeqi (i32 IntRegs:$src1), u8ImmPred:$src2),
bb:$offset)>, bb:$offset)>,
Requires<[HasV4T]>; Requires<[HasV4T]>;
@ -2809,7 +2773,7 @@ def DEC_CONST_BYTE : SDNodeXForm<imm, [{
// if (!Pd.new) Rd=#0 // if (!Pd.new) Rd=#0
def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)), def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
u8ExtPred:$u8)))), u8ExtPred:$u8)))),
(i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs), (i32 (TFR_condset_ii (i1 (A4_cmpbeqi (i32 IntRegs:$Rs),
(u8ExtPred:$u8))), (u8ExtPred:$u8))),
1, 0))>, 1, 0))>,
Requires<[HasV4T]>; Requires<[HasV4T]>;
@ -2822,7 +2786,7 @@ def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
// if (!Pd.new) Rd=#1 // if (!Pd.new) Rd=#1
def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)), def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
u8ExtPred:$u8)))), u8ExtPred:$u8)))),
(i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs), (i32 (TFR_condset_ii (i1 (A4_cmpbeqi (i32 IntRegs:$Rs),
(u8ExtPred:$u8))), (u8ExtPred:$u8))),
0, 1))>, 0, 1))>,
Requires<[HasV4T]>; Requires<[HasV4T]>;