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Cyle -> Cycle; NFCI 

llvm-svn: 297846
This commit is contained in:
Sanjay Patel 2017-03-15 15:37:42 +00:00
parent 8c7d28b2f1
commit fa929a2134
3 changed files with 8 additions and 8 deletions
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4
llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
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@ -893,7 +893,7 @@ bool R600InstrInfo::isPredicable(const MachineInstr &MI) const {
bool bool
R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
unsigned NumCyles, unsigned NumCycles,
unsigned ExtraPredCycles, unsigned ExtraPredCycles,
BranchProbability Probability) const{ BranchProbability Probability) const{
return true; return true;
@ -912,7 +912,7 @@ R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
bool bool
R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB, R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
unsigned NumCyles, unsigned NumCycles,
BranchProbability Probability) BranchProbability Probability)
const { const {
return true; return true;

4
llvm/lib/Target/AMDGPU/R600InstrInfo.h
View File

@ -179,10 +179,10 @@ public:
bool isPredicable(const MachineInstr &MI) const override; bool isPredicable(const MachineInstr &MI) const override;
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
BranchProbability Probability) const override; BranchProbability Probability) const override;
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
unsigned ExtraPredCycles, unsigned ExtraPredCycles,
BranchProbability Probability) const override ; BranchProbability Probability) const override ;

8
llvm/lib/Target/ARM/ARMScheduleSwift.td
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@ -168,10 +168,10 @@ let SchedModel = SwiftModel in {
def : InstRW<[SwiftWriteP01OneCycle2x_load], def : InstRW<[SwiftWriteP01OneCycle2x_load],
(instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>; (instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>;
def SwiftWriteP0TwoCyleTwoUops : WriteSequence<[SwiftWriteP0OneCycle], 2>; def SwiftWriteP0TwoCycleTwoUops : WriteSequence<[SwiftWriteP0OneCycle], 2>;
def SwiftPredP0OneOrTwoCycle : SchedWriteVariant<[ def SwiftPredP0OneOrTwoCycle : SchedWriteVariant<[
SchedVar<IsPredicatedPred, [ SwiftWriteP0TwoCyleTwoUops ]>, SchedVar<IsPredicatedPred, [ SwiftWriteP0TwoCycleTwoUops ]>,
SchedVar<NoSchedPred, [ SwiftWriteP0OneCycle ]> SchedVar<NoSchedPred, [ SwiftWriteP0OneCycle ]>
]>; ]>;
@ -324,7 +324,7 @@ let SchedModel = SwiftModel in {
let Latency = 3; let Latency = 3;
let NumMicroOps = 2; let NumMicroOps = 2;
} }
def SwiftWriteP2P01FourCyle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { def SwiftWriteP2P01FourCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
let Latency = 4; let Latency = 4;
let NumMicroOps = 2; let NumMicroOps = 2;
} }
@ -357,7 +357,7 @@ let SchedModel = SwiftModel in {
"tLDR(r|i|spi|pci|pciASM)")>; "tLDR(r|i|spi|pci|pciASM)")>;
def : InstRW<[SwiftWriteP2ThreeCycle], def : InstRW<[SwiftWriteP2ThreeCycle],
(instregex "LDRH$", "PICLDR$", "PICLDR(H|B)$", "LDRcp$")>; (instregex "LDRH$", "PICLDR$", "PICLDR(H|B)$", "LDRcp$")>;
def : InstRW<[SwiftWriteP2P01FourCyle], def : InstRW<[SwiftWriteP2P01FourCycle],
(instregex "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$", (instregex "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$",
"t2LDRpci_pic", "tLDRS(B|H)")>; "t2LDRpci_pic", "tLDRS(B|H)")>;
def : InstRW<[SwiftWriteP2P01ThreeCycle, SwiftWrBackOne], def : InstRW<[SwiftWriteP2P01ThreeCycle, SwiftWrBackOne],