forked from OSchip/llvm-project
Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types.
This avoids moving each element to the integer register file and calling __divsi3 etc. on it. llvm-svn: 125402
This commit is contained in:
Nate Begeman
parent
6cc8f5d83c
commit
fa62d50481
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@ -454,6 +454,11 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::MUL, MVT::v8i16, Custom);
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setOperationAction(ISD::MUL, MVT::v4i32, Custom);
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setOperationAction(ISD::MUL, MVT::v2i64, Custom);
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// Custom handling for some vector types to avoid expensive expansions
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setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
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setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
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setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
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setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
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setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
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setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
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@ -4285,6 +4290,181 @@ static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
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}
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static SDValue
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LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
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// Convert to float
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// float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
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// float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
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X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
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Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
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X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
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Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
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// Get reciprocal estimate.
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// float4 recip = vrecpeq_f32(yf);
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Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
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// Because char has a smaller range than uchar, we can actually get away
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// without any newton steps. This requires that we use a weird bias
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// of 0xb000, however (again, this has been exhaustively tested).
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// float4 result = as_float4(as_int4(xf*recip) + 0xb000);
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X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
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X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
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Y = DAG.getConstant(0xb000, MVT::i32);
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Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
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X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
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X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
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// Convert back to short.
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X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
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X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
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return X;
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}
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static SDValue
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LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
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SDValue N2;
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// Convert to float.
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// float4 yf = vcvt_f32_s32(vmovl_s16(y));
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// float4 xf = vcvt_f32_s32(vmovl_s16(x));
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N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
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N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
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N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
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N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
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// Use reciprocal estimate and one refinement step.
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// float4 recip = vrecpeq_f32(yf);
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// recip *= vrecpsq_f32(yf, recip);
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N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
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N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
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N1, N2);
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N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
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// Because short has a smaller range than ushort, we can actually get away
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// with only a single newton step. This requires that we use a weird bias
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// of 89, however (again, this has been exhaustively tested).
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// float4 result = as_float4(as_int4(xf*recip) + 89);
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N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
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N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
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N1 = DAG.getConstant(89, MVT::i32);
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N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
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N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
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N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
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// Convert back to integer and return.
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// return vmovn_s32(vcvt_s32_f32(result));
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N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
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N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
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return N0;
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}
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static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
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EVT VT = Op.getValueType();
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assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
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"unexpected type for custom-lowering ISD::SDIV");
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DebugLoc dl = Op.getDebugLoc();
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SDValue N0 = Op.getOperand(0);
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SDValue N1 = Op.getOperand(1);
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SDValue N2, N3;
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if (VT == MVT::v8i8) {
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N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
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N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
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N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
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DAG.getIntPtrConstant(4));
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N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
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DAG.getIntPtrConstant(4));
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N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
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DAG.getIntPtrConstant(0));
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N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
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DAG.getIntPtrConstant(0));
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N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
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N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
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N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
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N0 = LowerCONCAT_VECTORS(N0, DAG);
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N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
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return N0;
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}
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return LowerSDIV_v4i16(N0, N1, dl, DAG);
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}
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static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
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EVT VT = Op.getValueType();
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assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
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"unexpected type for custom-lowering ISD::UDIV");
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DebugLoc dl = Op.getDebugLoc();
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SDValue N0 = Op.getOperand(0);
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SDValue N1 = Op.getOperand(1);
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SDValue N2, N3;
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if (VT == MVT::v8i8) {
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N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
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N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
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N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
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DAG.getIntPtrConstant(4));
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N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
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DAG.getIntPtrConstant(4));
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N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
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DAG.getIntPtrConstant(0));
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N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
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DAG.getIntPtrConstant(0));
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N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
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N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
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N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
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N0 = LowerCONCAT_VECTORS(N0, DAG);
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N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
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DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
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N0);
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return N0;
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}
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// v4i16 sdiv ... Convert to float.
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// float4 yf = vcvt_f32_s32(vmovl_u16(y));
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// float4 xf = vcvt_f32_s32(vmovl_u16(x));
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N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
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N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
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N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
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N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
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// Use reciprocal estimate and two refinement steps.
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// float4 recip = vrecpeq_f32(yf);
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// recip *= vrecpsq_f32(yf, recip);
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// recip *= vrecpsq_f32(yf, recip);
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N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
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N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
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N1, N2);
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N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
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N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
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DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
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N1, N2);
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N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
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// Simply multiplying by the reciprocal estimate can leave us a few ulps
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// too low, so we add 2 ulps (exhaustive testing shows that this is enough,
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// and that it will never cause us to return an answer too large).
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// float4 result = as_float4(as_int4(xf*recip) + 89);
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N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
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N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
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N1 = DAG.getConstant(2, MVT::i32);
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N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
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N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
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N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
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// Convert back to integer and return.
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// return vmovn_u32(vcvt_s32_f32(result));
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N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
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N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
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return N0;
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}
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SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default: llvm_unreachable("Don't know how to custom lower this!");
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@ -4329,6 +4509,8 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
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case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
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case ISD::MUL: return LowerMUL(Op, DAG);
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case ISD::SDIV: return LowerSDIV(Op, DAG);
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case ISD::UDIV: return LowerUDIV(Op, DAG);
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}
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return SDValue();
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}
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@ -0,0 +1,48 @@
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vrecpe.f32
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;CHECK: vrecpe.f32
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;CHECK: vmovn.i32
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;CHECK: vmovn.i32
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;CHECK: vmovn.i16
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = sdiv <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vrecpe.f32
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;CHECK: vrecps.f32
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;CHECK: vrecpe.f32
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;CHECK: vrecps.f32
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;CHECK: vmovn.i32
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;CHECK: vmovn.i32
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;CHECK: vqmovun.s16
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = udiv <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vrecpe.f32
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;CHECK: vrecps.f32
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;CHECK: vmovn.i32
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = sdiv <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <4 x i16> @udivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vrecpe.f32
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;CHECK: vrecps.f32
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;CHECK: vrecps.f32
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;CHECK: vmovn.i32
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = udiv <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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