forked from OSchip/llvm-project
[X86] Improved target combine rules for selecting horizontal add/sub.
This patch slightly changes the algorithm introduced at revision 210477 to fix a problem where the algorithm was producing incorrect code for the VEX.256 encoded versions of horizontal add/sub. For these cases, we now try to split the two 256-bit vectors into 128-bit chunks before emitting horizontal add/sub dag nodes. Added a new test case into haddsub-2.ll. llvm-svn: 210545
This commit is contained in:
Andrea Di Biagio
parent
d172270c44
commit
fa508af0fe
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@ -6061,9 +6061,9 @@ static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
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// Try to match a horizontal ADD or SUB.
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if (((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) ||
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((VT == MVT::v8f32 || VT == MVT::v4f64) && Subtarget->hasAVX()) ||
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((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) ||
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((VT == MVT::v8i32 || VT == MVT::v16i16) && Subtarget->hasAVX2())) {
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((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
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VT == MVT::v16i16) && Subtarget->hasAVX())) {
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unsigned NumOperands = N->getNumOperands();
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unsigned Opcode = N->getOperand(0)->getOpcode();
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bool isCommutable = false;
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@ -6131,6 +6131,24 @@ static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
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case ISD::FSUB : NewOpcode = X86ISD::FHSUB; break;
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}
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if (VT.is256BitVector()) {
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SDLoc dl(N);
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// Convert this sequence into two horizontal add/sub followed
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// by a concat vector.
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SDValue InVec0_LO = Extract128BitVector(InVec0, 0, DAG, dl);
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SDValue InVec0_HI =
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Extract128BitVector(InVec0, NumOperands/2, DAG, dl);
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SDValue InVec1_LO = Extract128BitVector(InVec1, 0, DAG, dl);
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SDValue InVec1_HI =
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Extract128BitVector(InVec1, NumOperands/2, DAG, dl);
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EVT NewVT = InVec0_LO.getValueType();
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SDValue LO = DAG.getNode(NewOpcode, dl, NewVT, InVec0_LO, InVec0_HI);
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SDValue HI = DAG.getNode(NewOpcode, dl, NewVT, InVec1_LO, InVec1_HI);
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return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LO, HI);
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}
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return DAG.getNode(NewOpcode, SDLoc(N), VT, InVec0, InVec1);
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}
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}
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@ -298,6 +298,8 @@ define <4 x double> @avx_vhadd_pd_test(<4 x double> %A, <4 x double> %B) {
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; SSSE3: haddpd
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; SSSE3: haddpd
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; AVX: vhaddpd
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; AVX: vhaddpd
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; AVX2: vhaddpd
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; AVX2: vhaddpd
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; CHECK: ret
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@ -327,6 +329,8 @@ define <4 x double> @avx_vhsub_pd_test(<4 x double> %A, <4 x double> %B) {
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; SSSE3: hsubpd
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; SSSE3-NEXT: hsubpd
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; AVX: vhsubpd
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; AVX: vhsubpd
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; AVX2: vhsubpd
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; AVX2: vhsubpd
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; CHECK: ret
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@ -370,7 +374,87 @@ define <8 x i32> @avx2_vphadd_d_test(<8 x i32> %A, <8 x i32> %B) {
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; SSE3-NOT: phaddd
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; SSSE3: phaddd
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; SSSE3-NEXT: phaddd
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; AVX-NOT: vphaddd
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; AVX: vphaddd
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; AVX: vphaddd
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; AVX2: vphaddd
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; AVX2: vphaddd
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; CHECK: ret
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define <16 x i16> @avx2_vphadd_w_test(<16 x i16> %a, <16 x i16> %b) {
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%vecext = extractelement <16 x i16> %a, i32 0
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%vecext1 = extractelement <16 x i16> %a, i32 1
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%add = add i16 %vecext, %vecext1
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%vecinit = insertelement <16 x i16> undef, i16 %add, i32 0
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%vecext4 = extractelement <16 x i16> %a, i32 2
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%vecext6 = extractelement <16 x i16> %a, i32 3
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%add8 = add i16 %vecext4, %vecext6
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%vecinit10 = insertelement <16 x i16> %vecinit, i16 %add8, i32 1
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%vecext11 = extractelement <16 x i16> %a, i32 4
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%vecext13 = extractelement <16 x i16> %a, i32 5
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%add15 = add i16 %vecext11, %vecext13
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%vecinit17 = insertelement <16 x i16> %vecinit10, i16 %add15, i32 2
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%vecext18 = extractelement <16 x i16> %a, i32 6
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%vecext20 = extractelement <16 x i16> %a, i32 7
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%add22 = add i16 %vecext18, %vecext20
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%vecinit24 = insertelement <16 x i16> %vecinit17, i16 %add22, i32 3
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%vecext25 = extractelement <16 x i16> %a, i32 8
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%vecext27 = extractelement <16 x i16> %a, i32 9
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%add29 = add i16 %vecext25, %vecext27
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%vecinit31 = insertelement <16 x i16> %vecinit24, i16 %add29, i32 4
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%vecext32 = extractelement <16 x i16> %a, i32 10
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%vecext34 = extractelement <16 x i16> %a, i32 11
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%add36 = add i16 %vecext32, %vecext34
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%vecinit38 = insertelement <16 x i16> %vecinit31, i16 %add36, i32 5
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%vecext39 = extractelement <16 x i16> %a, i32 12
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%vecext41 = extractelement <16 x i16> %a, i32 13
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%add43 = add i16 %vecext39, %vecext41
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%vecinit45 = insertelement <16 x i16> %vecinit38, i16 %add43, i32 6
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%vecext46 = extractelement <16 x i16> %a, i32 14
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%vecext48 = extractelement <16 x i16> %a, i32 15
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%add50 = add i16 %vecext46, %vecext48
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%vecinit52 = insertelement <16 x i16> %vecinit45, i16 %add50, i32 7
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%vecext53 = extractelement <16 x i16> %b, i32 0
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%vecext55 = extractelement <16 x i16> %b, i32 1
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%add57 = add i16 %vecext53, %vecext55
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%vecinit59 = insertelement <16 x i16> %vecinit52, i16 %add57, i32 8
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%vecext60 = extractelement <16 x i16> %b, i32 2
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%vecext62 = extractelement <16 x i16> %b, i32 3
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%add64 = add i16 %vecext60, %vecext62
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%vecinit66 = insertelement <16 x i16> %vecinit59, i16 %add64, i32 9
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%vecext67 = extractelement <16 x i16> %b, i32 4
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%vecext69 = extractelement <16 x i16> %b, i32 5
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%add71 = add i16 %vecext67, %vecext69
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%vecinit73 = insertelement <16 x i16> %vecinit66, i16 %add71, i32 10
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%vecext74 = extractelement <16 x i16> %b, i32 6
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%vecext76 = extractelement <16 x i16> %b, i32 7
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%add78 = add i16 %vecext74, %vecext76
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%vecinit80 = insertelement <16 x i16> %vecinit73, i16 %add78, i32 11
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%vecext81 = extractelement <16 x i16> %b, i32 8
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%vecext83 = extractelement <16 x i16> %b, i32 9
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%add85 = add i16 %vecext81, %vecext83
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%vecinit87 = insertelement <16 x i16> %vecinit80, i16 %add85, i32 12
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%vecext88 = extractelement <16 x i16> %b, i32 10
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%vecext90 = extractelement <16 x i16> %b, i32 11
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%add92 = add i16 %vecext88, %vecext90
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%vecinit94 = insertelement <16 x i16> %vecinit87, i16 %add92, i32 13
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%vecext95 = extractelement <16 x i16> %b, i32 12
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%vecext97 = extractelement <16 x i16> %b, i32 13
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%add99 = add i16 %vecext95, %vecext97
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%vecinit101 = insertelement <16 x i16> %vecinit94, i16 %add99, i32 14
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%vecext102 = extractelement <16 x i16> %b, i32 14
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%vecext104 = extractelement <16 x i16> %b, i32 15
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%add106 = add i16 %vecext102, %vecext104
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%vecinit108 = insertelement <16 x i16> %vecinit101, i16 %add106, i32 15
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ret <16 x i16> %vecinit108
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}
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; CHECK-LABEL: avx2_vphadd_w_test
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; SSE3-NOT: phaddw
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; SSSE3: phaddw
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; SSSE3-NEXT: phaddw
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; AVX: vphaddw
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; AVX: vphaddw
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; AVX2: vphaddw
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; AVX2: vphaddw
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; CHECK: ret
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