forked from OSchip/llvm-project
Revert r351938 "[ARM] Alter the register allocation order for minsize on Thumb2"
This change caused fatal backend errors when compiling a file in libvpx for Android. llvm-svn: 351979
This commit is contained in:
Reid Kleckner
parent
a010cf615a
commit
f9ebacfd29
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@ -204,21 +204,13 @@ def FPINST2 : ARMReg<10, "fpinst2">;
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def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
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SP, LR, PC)> {
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// Allocate LR as the first CSR since it is always saved anyway.
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// For Thumb2, using LR would force 32bit Thumb2 instructions, not the smaller
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// Thumb1 ones. It is a little better for codesize on average to use the
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// default order.
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// For Thumb1 mode, we don't want to allocate hi regs at all, as we don't
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// know how to spill them. If we make our prologue/epilogue code smarter at
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// some point, we can go back to using the above allocation orders for the
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// Thumb1 instructions that know how to use hi regs.
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let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
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let AltOrderSelect = [{
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if (MF.getSubtarget<ARMSubtarget>().isThumb1Only())
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return 2;
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if (MF.getSubtarget<ARMSubtarget>().isThumb2() &&
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MF.getFunction().optForMinSize())
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return 0;
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return 1;
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return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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let DiagnosticString = "operand must be a register in range [r0, r15]";
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}
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@ -229,12 +221,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
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def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
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let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
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let AltOrderSelect = [{
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if (MF.getSubtarget<ARMSubtarget>().isThumb1Only())
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return 2;
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if (MF.getSubtarget<ARMSubtarget>().isThumb2() &&
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MF.getFunction().optForMinSize())
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return 0;
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return 1;
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return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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let DiagnosticString = "operand must be a register in range [r0, r14]";
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}
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@ -245,12 +232,7 @@ def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
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def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
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let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
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let AltOrderSelect = [{
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if (MF.getSubtarget<ARMSubtarget>().isThumb1Only())
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return 2;
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if (MF.getSubtarget<ARMSubtarget>().isThumb2() &&
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MF.getFunction().optForMinSize())
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return 0;
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return 1;
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return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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let DiagnosticString = "operand must be a register in range [r0, r14] or apsr_nzcv";
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}
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@ -271,12 +253,7 @@ def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)> {
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def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
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let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
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let AltOrderSelect = [{
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if (MF.getSubtarget<ARMSubtarget>().isThumb1Only())
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return 2;
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if (MF.getSubtarget<ARMSubtarget>().isThumb2() &&
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MF.getFunction().optForMinSize())
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return 0;
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return 1;
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return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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let DiagnosticType = "rGPR";
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}
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@ -1,106 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s
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define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) #0 {
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; CHECK-LABEL: test:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: adds r4, r3, r0
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; CHECK-NEXT: add.w r12, r2, r1
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; CHECK-NEXT: add r0, r1
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; CHECK-NEXT: adds r1, r3, r2
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; CHECK-NEXT: mul r4, r4, r12
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; CHECK-NEXT: mla r0, r1, r0, r4
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; CHECK-NEXT: pop {r4, pc}
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entry:
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%add = add nsw i32 %b, %a
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%add1 = add nsw i32 %d, %c
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%mul = mul nsw i32 %add1, %add
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%add2 = add nsw i32 %d, %a
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%add3 = add nsw i32 %c, %b
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%mul4 = mul nsw i32 %add2, %add3
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%add5 = add nsw i32 %mul, %mul4
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ret i32 %add5
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}
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define void @loop(i32 %I, i8* %A, i8* %B) #0 {
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; CHECK-LABEL: loop:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: b .LBB1_2
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; CHECK-NEXT: .LBB1_1: @ %for.body
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; CHECK-NEXT: @ in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: add.w r4, r12, r12, lsl #1
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; CHECK-NEXT: add.w r3, r2, r12, lsl #2
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; CHECK-NEXT: add r4, r1
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; CHECK-NEXT: add.w r12, r12, #1
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; CHECK-NEXT: ldrsb.w r6, [r4, #2]
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; CHECK-NEXT: ldrsb.w r5, [r4]
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; CHECK-NEXT: mov r7, r6
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; CHECK-NEXT: cmp r5, r6
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; CHECK-NEXT: it gt
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; CHECK-NEXT: movgt r7, r5
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; CHECK-NEXT: ldrsb.w r4, [r4, #1]
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; CHECK-NEXT: cmp r7, r4
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; CHECK-NEXT: it le
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; CHECK-NEXT: movle r7, r4
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; CHECK-NEXT: subs r4, r7, r4
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; CHECK-NEXT: subs r6, r7, r6
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; CHECK-NEXT: strb r6, [r3, #3]
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; CHECK-NEXT: strb r4, [r3, #2]
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; CHECK-NEXT: subs r4, r7, r5
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; CHECK-NEXT: strb r4, [r3, #1]
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; CHECK-NEXT: mvns r4, r7
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; CHECK-NEXT: strb r4, [r3]
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; CHECK-NEXT: .LBB1_2: @ %for.cond
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmp r12, r0
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; CHECK-NEXT: blt .LBB1_1
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; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup
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; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
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entry:
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br label %for.cond
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for.cond: ; preds = %for.body, %entry
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%A.addr.0 = phi i8* [ %A, %entry ], [ %incdec.ptr2, %for.body ]
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%B.addr.0 = phi i8* [ %B, %entry ], [ %incdec.ptr47, %for.body ]
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%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%cmp = icmp slt i32 %i.0, %I
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.body: ; preds = %for.cond
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%incdec.ptr = getelementptr inbounds i8, i8* %A.addr.0, i32 1
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%0 = load i8, i8* %A.addr.0, align 1
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%incdec.ptr1 = getelementptr inbounds i8, i8* %A.addr.0, i32 2
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%1 = load i8, i8* %incdec.ptr, align 1
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%incdec.ptr2 = getelementptr inbounds i8, i8* %A.addr.0, i32 3
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%2 = load i8, i8* %incdec.ptr1, align 1
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%3 = icmp sgt i8 %0, %2
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%4 = select i1 %3, i8 %0, i8 %2
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%5 = icmp sgt i8 %4, %1
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%6 = select i1 %5, i8 %4, i8 %1
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%7 = xor i8 %6, -1
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%sub34 = sub i8 %6, %0
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%sub38 = sub i8 %6, %1
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%sub42 = sub i8 %6, %2
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%incdec.ptr44 = getelementptr inbounds i8, i8* %B.addr.0, i32 1
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store i8 %7, i8* %B.addr.0, align 1
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%incdec.ptr45 = getelementptr inbounds i8, i8* %B.addr.0, i32 2
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store i8 %sub34, i8* %incdec.ptr44, align 1
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%incdec.ptr46 = getelementptr inbounds i8, i8* %B.addr.0, i32 3
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store i8 %sub38, i8* %incdec.ptr45, align 1
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%incdec.ptr47 = getelementptr inbounds i8, i8* %B.addr.0, i32 4
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store i8 %sub42, i8* %incdec.ptr46, align 1
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%inc = add nuw nsw i32 %i.0, 1
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br label %for.cond
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for.cond.cleanup: ; preds = %for.cond
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ret void
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}
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attributes #0 = { minsize optsize }
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