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[Hexagon] Add patterns for truncating HVX vector types 

Only non-bool vectors.

llvm-svn: 321895
This commit is contained in:
Krzysztof Parzyszek 2018-01-05 20:48:03 +00:00
parent 9d0c6355a0
commit f9d01a12d1
2 changed files with 23 additions and 0 deletions
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5
llvm/lib/Target/Hexagon/HexagonPatterns.td
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@ -3019,4 +3019,9 @@ let Predicates = [UseHVX] in {
def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i16)),
(V6_vasrh (V6_vaslh HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
}
def: Pat<(VecI8 (trunc HWI16:$Vss)),
(V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
def: Pat<(VecI16 (trunc HWI32:$Vss)),
(V6_vpackeh (HiVec $Vss), (LoVec $Vss))>;
}

18
llvm/test/CodeGen/Hexagon/autohvx/isel-truncate.ll Normal file
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@ -0,0 +1,18 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that this compiles successfully.
; CHECK: vpacke
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
; Function Attrs: norecurse nounwind
define void @fred() #0 {
b0:
%v1 = select <16 x i1> undef, <16 x i32> undef, <16 x i32> zeroinitializer
%v2 = trunc <16 x i32> %v1 to <16 x i16>
store <16 x i16> %v2, <16 x i16>* undef, align 2
ret void
}
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }