From f9b2e3c68acb7a8188b5bd735216d207279bae9d Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Thu, 15 Apr 2010 05:28:43 +0000 Subject: [PATCH] add a simple dag combine to replace trivial shl+lshr with and. This happens with the store->load narrowing stuff. llvm-svn: 101348 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 +++++++++ llvm/test/CodeGen/ARM/sbfx.ll | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 671c50770564..5974aff03ca0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2735,6 +2735,15 @@ SDValue DAGCombiner::visitSRL(SDNode *N) { return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), DAG.getConstant(c1 + c2, N1.getValueType())); } + + // fold (srl (shl x, c), c) -> (and x, cst2) + if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && + N0.getValueSizeInBits() <= 64) { + uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), + DAG.getConstant(~0ULL >> ShAmt, VT)); + } + // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { diff --git a/llvm/test/CodeGen/ARM/sbfx.ll b/llvm/test/CodeGen/ARM/sbfx.ll index 6f1d87d2c17b..d29693e4cf92 100644 --- a/llvm/test/CodeGen/ARM/sbfx.ll +++ b/llvm/test/CodeGen/ARM/sbfx.ll @@ -12,7 +12,7 @@ entry: define i32 @f2(i32 %a) { entry: ; CHECK: f2: -; CHECK: ubfx r0, r0, #0, #20 +; CHECK: bfc r0, #20, #12 %tmp = shl i32 %a, 12 %tmp2 = lshr i32 %tmp, 12 ret i32 %tmp2