forked from OSchip/llvm-project
[mips][microMIPS] Implement SWM16 and LWM16 instructions
Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
This commit is contained in:
Zoran Jovanovic
parent
56a6a7d3bd
commit
f9a02500b6
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@ -809,6 +809,29 @@ public:
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bool isMemWithGRPMM16Base() const {
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return isMem() && getMemBase()->isMM16AsmReg();
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}
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template <unsigned Bits> bool isMemWithUimmOffsetSP() const {
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return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
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&& getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP);
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}
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bool isRegList16() const {
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if (!isRegList())
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return false;
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int Size = RegList.List->size();
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if (Size < 2 || Size > 5 || *RegList.List->begin() != Mips::S0 ||
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RegList.List->back() != Mips::RA)
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return false;
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int PrevReg = *RegList.List->begin();
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for (int i = 1; i < Size - 1; i++) {
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int Reg = (*(RegList.List))[i];
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if ( Reg != PrevReg + 1)
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return false;
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PrevReg = Reg;
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}
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return true;
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}
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bool isInvNum() const { return Kind == k_Immediate; }
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bool isLSAImm() const {
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if (!isConstantImm())
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@ -380,6 +380,10 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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namespace llvm {
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extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
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TheMips64elTarget;
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@ -1609,3 +1613,23 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
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unsigned RegNum;
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unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
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// Empty register lists are not allowed.
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if (RegLst == 0)
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return MCDisassembler::Fail;
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RegNum = RegLst & 0x3;
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for (unsigned i = 0; i < RegNum - 1; i++)
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Inst.addOperand(MCOperand::CreateReg(Regs[i]));
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Inst.addOperand(MCOperand::CreateReg(Mips::RA));
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return MCDisassembler::Success;
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}
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@ -233,6 +233,8 @@ printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
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break;
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case Mips::SWM32_MM:
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case Mips::LWM32_MM:
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case Mips::SWM16_MM:
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case Mips::LWM16_MM:
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opNum = MI->getNumOperands() - 2;
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break;
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}
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@ -699,6 +699,30 @@ getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
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return (OffBits & 0x0FFF) | RegBits;
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}
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unsigned MipsMCCodeEmitter::
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getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// opNum can be invalid if instruction had reglist as operand
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// MemOperand is always last operand of instruction (base + offset)
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switch (MI.getOpcode()) {
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default:
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break;
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case Mips::SWM16_MM:
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case Mips::LWM16_MM:
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OpNo = MI.getNumOperands() - 2;
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break;
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}
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// Offset is encoded in bits 4-0.
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assert(MI.getOperand(OpNo).isReg());
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// Base register is always SP - thus it is not encoded.
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assert(MI.getOperand(OpNo+1).isImm());
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unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
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return ((OffBits >> 2) & 0x0F);
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}
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unsigned
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MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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@ -830,4 +854,11 @@ MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
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return res;
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}
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unsigned
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MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return (MI.getNumOperands() - 4);
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}
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#include "MipsGenMCCodeEmitter.inc"
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@ -154,6 +154,9 @@ public:
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unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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@ -187,6 +190,10 @@ public:
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unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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}; // class MipsMCCodeEmitter
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} // namespace llvm.
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@ -838,3 +838,15 @@ class LWM_FM_MM<bits<4> funct> : MMArch {
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let Inst{15-12} = funct;
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let Inst{11-0} = addr{11-0};
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}
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class LWM_FM_MM16<bits<4> funct> : MMArch {
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bits<2> rt;
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bits<4> addr;
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bits<16> Inst;
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let Inst{15-10} = 0x11;
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let Inst{9-6} = funct;
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let Inst{5-4} = rt;
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let Inst{3-0} = addr;
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}
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@ -86,6 +86,22 @@ def mem_mm_12 : Operand<i32> {
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let OperandType = "OPERAND_MEMORY";
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}
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def MipsMemUimm4AsmOperand : AsmOperandClass {
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let Name = "MemOffsetUimm4";
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let SuperClasses = [MipsMemAsmOperand];
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let RenderMethod = "addMemOperands";
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let ParserMethod = "parseMemOperand";
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let PredicateMethod = "isMemWithUimmOffsetSP<6>";
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}
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def mem_mm_4sp : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops GPR32, uimm8);
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let EncoderMethod = "getMemEncodingMMImm4sp";
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let ParserMatchClass = MipsMemUimm4AsmOperand;
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let OperandType = "OPERAND_MEMORY";
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}
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def jmptarget_mm : Operand<OtherVT> {
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let EncoderMethod = "getJumpTargetOpValueMM";
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}
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@ -339,6 +355,20 @@ def reglist : Operand<i32> {
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let DecoderMethod = "DecodeRegListOperand";
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}
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def RegList16AsmOperand : AsmOperandClass {
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let Name = "RegList16";
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let ParserMethod = "parseRegisterList";
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let PredicateMethod = "isRegList16";
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let RenderMethod = "addRegListOperands";
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}
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def reglist16 : Operand<i32> {
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let EncoderMethod = "getRegisterListOpValue16";
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let DecoderMethod = "DecodeRegListOperand16";
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let PrintMethod = "printRegisterList";
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let ParserMatchClass = RegList16AsmOperand;
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}
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class StoreMultMM<string opstr,
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InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
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InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
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@ -355,6 +385,22 @@ class LoadMultMM<string opstr,
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let mayLoad = 1;
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}
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class StoreMultMM16<string opstr,
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InstrItinClass Itin = NoItinerary,
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ComplexPattern Addr = addr> :
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MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
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let mayStore = 1;
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}
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class LoadMultMM16<string opstr,
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InstrItinClass Itin = NoItinerary,
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ComplexPattern Addr = addr> :
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MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
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let mayLoad = 1;
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}
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def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
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ARITH_FM_MM16<0>;
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def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
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@ -504,6 +550,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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/// Load and Store Instructions - multiple
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def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
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def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
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def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
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def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
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/// Move Conditional
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def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
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@ -22,6 +22,15 @@
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li16 $4, -2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
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addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
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lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
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lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
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lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
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lwm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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lwm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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lwm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
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swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
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swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
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lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
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lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
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lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
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@ -29,6 +29,8 @@
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# CHECK-EL: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x24,0x23,0x08,0x50]
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# CHECK-EL: swm32 $16, $17, 8($4) # encoding: [0x44,0x20,0x08,0xd0]
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# CHECK-EL: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x84,0x20,0x08,0xd0]
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# CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
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# CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45]
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#------------------------------------------------------------------------------
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# Big endian
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#------------------------------------------------------------------------------
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@ -52,6 +54,8 @@
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# CHECK-EB: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
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# CHECK-EB: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
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# CHECK-EB: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
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# CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
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# CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
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lb $5, 8($4)
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lbu $6, 8($4)
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lh $2, 8($4)
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@ -72,3 +76,5 @@
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lwm32 $16-$23, $30 - $31, 8($4)
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swm32 $16, $17, 8($4)
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swm32 $16 - $19, 8($4)
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lwm16 $16, $17, $ra, 8($sp)
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swm16 $16, $17, $ra, 8($sp)
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