maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

AMDGPU: Remove register operand from si_mask_branch 

It isn't used for anything, and is also misleading since
it could be spilled at the end of the block, so it can't be relied
on. There ends up being a verifier error about using an undefined
register since the spill kills the register.

llvm-svn: 279899
This commit is contained in:
Matt Arsenault 2016-08-27 00:42:21 +00:00
parent 42034d009d
commit f98a596954
2 changed files with 3 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/AMDGPU/SIInstructions.td
View File

@ -1803,7 +1803,7 @@ let hasSideEffects = 1 in {
// Dummy terminator instruction to use after control flow instructions // Dummy terminator instruction to use after control flow instructions
// replaced with exec mask operations. // replaced with exec mask operations.
def SI_MASK_BRANCH : PseudoInstSI < def SI_MASK_BRANCH : PseudoInstSI <
(outs), (ins brtarget:$target, SReg_64:$dst)> { (outs), (ins brtarget:$target)> {
let isBranch = 0; let isBranch = 0;
let isTerminator = 1; let isTerminator = 1;
let isBarrier = 0; let isBarrier = 0;

6
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
View File

@ -136,8 +136,7 @@ void SILowerControlFlow::emitIf(MachineInstr &MI) {
// be used later when inserting skips. // be used later when inserting skips.
MachineInstr *NewBr = MachineInstr *NewBr =
BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_MASK_BRANCH)) BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
.addOperand(MI.getOperand(2)) .addOperand(MI.getOperand(2));
.addReg(SaveExecReg, getKillRegState(SaveExec.isKill()));
if (!LIS) { if (!LIS) {
MI.eraseFromParent(); MI.eraseFromParent();
@ -196,8 +195,7 @@ void SILowerControlFlow::emitElse(MachineInstr &MI) {
// Insert a pseudo terminator to help keep the verifier happy. // Insert a pseudo terminator to help keep the verifier happy.
MachineInstr *Branch = MachineInstr *Branch =
BuildMI(MBB, Term, DL, TII->get(AMDGPU::SI_MASK_BRANCH)) BuildMI(MBB, Term, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
.addMBB(DestBB) .addMBB(DestBB);
.addReg(DstReg);
if (!LIS) { if (!LIS) {
MI.eraseFromParent(); MI.eraseFromParent();