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[Hexagon] Bitcast v4i16 to v8i8, unify no-op casts between scalar and HVX 

llvm-svn: 372616
This commit is contained in:
Krzysztof Parzyszek 2019-09-23 14:33:27 +00:00
parent a0d84ffee8
commit f97fdf5792
3 changed files with 38 additions and 26 deletions
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30
llvm/lib/Target/Hexagon/HexagonPatterns.td
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@ -344,6 +344,13 @@ multiclass MinMax_pats<InstHexagon PickT, InstHexagon PickS,
(PickS CmpPred:$Vs, CmpPred:$Vt)>;
}
// Bitcasts between same-size vector types are no-ops, except for the
// actual type change.
multiclass NopCast_pat<ValueType Ty1, ValueType Ty2, RegisterClass RC> {
def: Pat<(Ty1 (bitconvert (Ty2 RC:$Val))), (Ty1 RC:$Val)>;
def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>;
}
// Frags for commonly used SDNodes.
def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>;
@ -427,17 +434,18 @@ def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>;
def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>;
def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>;
multiclass Cast_pat<ValueType Ta, ValueType Tb, RegisterClass RC> {
def: Pat<(Tb (bitconvert (Ta RC:$Rs))), (Tb RC:$Rs)>;
def: Pat<(Ta (bitconvert (Tb RC:$Rs))), (Ta RC:$Rs)>;
}
// Bit convert vector types to integers.
defm: Cast_pat<v4i8, i32, IntRegs>;
defm: Cast_pat<v2i16, i32, IntRegs>;
defm: Cast_pat<v8i8, i64, DoubleRegs>;
defm: Cast_pat<v4i16, i64, DoubleRegs>;
defm: Cast_pat<v2i32, i64, DoubleRegs>;
// Bit convert 32- and 64-bit types.
// All of these are bitcastable to one another: i32, v2i16, v4i8.
defm: NopCast_pat<i32, v2i16, IntRegs>;
defm: NopCast_pat<i32, v4i8, IntRegs>;
defm: NopCast_pat<v2i16, v4i8, IntRegs>;
// All of these are bitcastable to one another: i64, v2i32, v4i16, v8i8.
defm: NopCast_pat<i64, v2i32, DoubleRegs>;
defm: NopCast_pat<i64, v4i16, DoubleRegs>;
defm: NopCast_pat<i64, v8i8, DoubleRegs>;
defm: NopCast_pat<v2i32, v4i16, DoubleRegs>;
defm: NopCast_pat<v2i32, v8i8, DoubleRegs>;
defm: NopCast_pat<v4i16, v8i8, DoubleRegs>;
// --(3) Extend/truncate -------------------------------------------------

21
llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
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@ -160,23 +160,14 @@ let Predicates = [UseHVX] in {
// Bitcasts between same-size vector types are no-ops, except for the
// actual type change.
class Bitcast<ValueType ResTy, ValueType InpTy, RegisterClass RC>
: Pat<(ResTy (bitconvert (InpTy RC:$Val))), (ResTy RC:$Val)>;
let Predicates = [UseHVX] in {
def: Bitcast<VecI8, VecI16, HvxVR>;
def: Bitcast<VecI8, VecI32, HvxVR>;
def: Bitcast<VecI16, VecI8, HvxVR>;
def: Bitcast<VecI16, VecI32, HvxVR>;
def: Bitcast<VecI32, VecI8, HvxVR>;
def: Bitcast<VecI32, VecI16, HvxVR>;
defm: NopCast_pat<VecI8, VecI16, HvxVR>;
defm: NopCast_pat<VecI8, VecI32, HvxVR>;
defm: NopCast_pat<VecI16, VecI32, HvxVR>;
def: Bitcast<VecPI8, VecPI16, HvxWR>;
def: Bitcast<VecPI8, VecPI32, HvxWR>;
def: Bitcast<VecPI16, VecPI8, HvxWR>;
def: Bitcast<VecPI16, VecPI32, HvxWR>;
def: Bitcast<VecPI32, VecPI8, HvxWR>;
def: Bitcast<VecPI32, VecPI16, HvxWR>;
defm: NopCast_pat<VecPI8, VecPI16, HvxWR>;
defm: NopCast_pat<VecPI8, VecPI32, HvxWR>;
defm: NopCast_pat<VecPI16, VecPI32, HvxWR>;
}
let Predicates = [UseHVX] in {

13
llvm/test/CodeGen/Hexagon/isel-bitcast-v8i8-v4i16.ll Normal file
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@ -0,0 +1,13 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that this doesn't fail to select instructions.
; CHECK: vsplath
define <8 x i8> @fred(i16 %a0) #0 {
%t0 = insertelement <4 x i16> undef, i16 %a0, i32 0
%t1 = shufflevector <4 x i16> %t0, <4 x i16> undef, <4 x i32> zeroinitializer
%t2 = bitcast <4 x i16> %t1 to <8 x i8>
ret <8 x i8> %t2
}
attributes #0 = { readnone nounwind "target-cpu"="hexagonv62" }