forked from OSchip/llvm-project
The r128103 fix to cope with the removal of addressing modes from the MC instructions
were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong. Fix the bad logic and add some sanity checking to detect bad instruction encoding; and add a test case. llvm-svn: 128186
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@ -1806,7 +1806,7 @@ static bool DisassembleVFPLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
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assert(NumOps >= 5 && "VFPLdStMulFrm expects NumOps >= 5");
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assert(NumOps >= 4 && "VFPLdStMulFrm expects NumOps >= 4");
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unsigned &OpIdx = NumOpsAdded;
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@ -1830,7 +1830,7 @@ static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
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MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
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OpIdx += 4;
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OpIdx += 3;
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bool isSPVFP = (Opcode == ARM::VLDMSIA || Opcode == ARM::VLDMSDB ||
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Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMSDB_UPD ||
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@ -1844,6 +1844,11 @@ static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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// Fill the variadic part of reglist.
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unsigned char Imm8 = insn & 0xFF;
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unsigned Regs = isSPVFP ? Imm8 : Imm8/2;
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// Apply some sanity checks before proceeding.
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if (Regs == 0 || (RegD + Regs) > 32 || (!isSPVFP && Regs > 16))
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return false;
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for (unsigned i = 0; i < Regs; ++i) {
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID,
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RegD + i)));
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@ -169,3 +169,6 @@
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# CHECK: vcmpe.f64 d8, #0
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0xc0 0x8b 0xb5 0xee
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# CHECK: vldmdb r2, {s7, s8, s9, s10, s11}
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0x05 0x3a 0x52 0xed
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