forked from OSchip/llvm-project
[AArch64][SVE] Add patterns for logical immediate operations.
Summary: Add pattern matching for the following SVE logical vector and immediate instructions: - and/bic, orr/orn, eor/eon. Reviewers: sdesmalen, huntergr, rengolin, efriedma, c-rhodes, mgudim, kmclaughlin Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits, amehsan Tags: #llvm Differential Revision: https://reviews.llvm.org/D71483
This commit is contained in:
Danilo Carvalho Grael
parent
f9a706a36a
commit
f933878991
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@ -1104,6 +1104,12 @@ class AdvSIMD_ScatterStore_VectorBase_Intrinsic
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],
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[IntrWriteMem, IntrArgMemOnly, ImmArg<3>]>;
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class AdvSIMD_1VectorArg_Imm64_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>,
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llvm_i64_ty],
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[IntrNoMem, ImmArg<1>]>;
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//
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// Loads
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//
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@ -1271,6 +1277,10 @@ def int_aarch64_sve_orns : AdvSIMD_Pred2VectorArg_Intrinsic;
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def int_aarch64_sve_nors : AdvSIMD_Pred2VectorArg_Intrinsic;
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def int_aarch64_sve_nands : AdvSIMD_Pred2VectorArg_Intrinsic;
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def int_aarch64_sve_orr_imm : AdvSIMD_1VectorArg_Imm64_Intrinsic;
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def int_aarch64_sve_eor_imm : AdvSIMD_1VectorArg_Imm64_Intrinsic;
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def int_aarch64_sve_and_imm : AdvSIMD_1VectorArg_Imm64_Intrinsic;
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//
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// Conversion
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//
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@ -164,6 +164,11 @@ public:
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return SelectSVEAddSubImm(N, VT, Imm, Shift);
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}
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template<MVT::SimpleValueType VT>
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bool SelectSVELogicalImm(SDValue N, SDValue &Imm) {
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return SelectSVELogicalImm(N, VT, Imm);
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}
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/// Form sequences of consecutive 64/128-bit registers for use in NEON
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/// instructions making use of a vector-list (e.g. ldN, tbl). Vecs must have
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/// between 1 and 4 elements. If it contains a single element that is returned
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@ -241,6 +246,8 @@ private:
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bool SelectCMP_SWAP(SDNode *N);
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bool SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SDValue &Shift);
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bool SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm);
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};
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} // end anonymous namespace
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@ -2851,6 +2858,35 @@ bool AArch64DAGToDAGISel::SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SD
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return false;
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}
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bool AArch64DAGToDAGISel::SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm) {
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if (auto CNode = dyn_cast<ConstantSDNode>(N)) {
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uint64_t ImmVal = CNode->getZExtValue();
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SDLoc DL(N);
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// Shift mask depending on type size.
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switch (VT.SimpleTy) {
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case MVT::i8:
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ImmVal &= 0xFF;
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ImmVal |= (ImmVal << 8);
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case MVT::i16:
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ImmVal &= 0xFFFF;
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ImmVal |= (ImmVal << 16);
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case MVT::i32:
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ImmVal &= 0xFFFFFFFF;
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ImmVal |= (ImmVal << 32);
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break;
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default:
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break;
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}
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uint64_t encoding;
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if (AArch64_AM::processLogicalImmediate(ImmVal, 64, encoding)) {
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Imm = CurDAG->getTargetConstant(encoding, DL, MVT::i64);
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return true;
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}
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}
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return false;
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}
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bool AArch64DAGToDAGISel::trySelectStackSlotTagP(SDNode *N) {
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// tagp(FrameIndex, IRGstack, tag_offset):
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@ -117,9 +117,9 @@ let Predicates = [HasSVE] in {
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defm EORV_VPZ : sve_int_reduce_2<0b001, "eorv", AArch64eorv_pred>;
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defm ANDV_VPZ : sve_int_reduce_2<0b010, "andv", AArch64andv_pred>;
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defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn">;
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defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">;
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defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">;
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defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn", int_aarch64_sve_orr_imm>;
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defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon", int_aarch64_sve_eor_imm>;
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defm AND_ZI : sve_int_log_imm<0b10, "and", "bic", int_aarch64_sve_and_imm>;
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defm SMAX_ZI : sve_int_arith_imm1<0b00, "smax", simm8>;
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defm SMIN_ZI : sve_int_arith_imm1<0b10, "smin", simm8>;
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@ -207,6 +207,12 @@ def SVEAddSubImm16Pat : ComplexPattern<i32, 2, "SelectSVEAddSubImm<MVT::i16>", [
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def SVEAddSubImm32Pat : ComplexPattern<i32, 2, "SelectSVEAddSubImm<MVT::i32>", []>;
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def SVEAddSubImm64Pat : ComplexPattern<i32, 2, "SelectSVEAddSubImm<MVT::i64>", []>;
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def SVELogicalImm8Pat : ComplexPattern<i64, 1, "SelectSVELogicalImm<MVT::i8>", []>;
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def SVELogicalImm16Pat : ComplexPattern<i64, 1, "SelectSVELogicalImm<MVT::i16>", []>;
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def SVELogicalImm32Pat : ComplexPattern<i64, 1, "SelectSVELogicalImm<MVT::i32>", []>;
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def SVELogicalImm64Pat : ComplexPattern<i64, 1, "SelectSVELogicalImm<MVT::i64>", []>;
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class SVEExactFPImm<string Suffix, string ValA, string ValB> : AsmOperandClass {
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let Name = "SVEExactFPImmOperand" # Suffix;
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let DiagnosticType = "Invalid" # Name;
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@ -298,6 +304,11 @@ class SVE_1_Op_Imm_OptLsl_Pat<ValueType vt, SDPatternOperator op, ZPRRegOp zprty
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: Pat<(vt (op (vt zprty:$Op1), (i32 (cpx i32:$imm, i32:$shift)))),
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(inst $Op1, i32:$imm, i32:$shift)>;
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class SVE_1_Op_Imm_Log_Pat<ValueType vt, SDPatternOperator op, ZPRRegOp zprty,
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ComplexPattern cpx, Instruction inst>
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: Pat<(vt (op (vt zprty:$Op1), (i64 (cpx i64:$imm)))),
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(inst $Op1, i64:$imm)>;
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class SVE_2_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
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ValueType vt2, Instruction inst>
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: Pat<(vtd (op vt1:$Op1, vt2:$Op2)),
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@ -1129,9 +1140,14 @@ class sve_int_log_imm<bits<2> opc, string asm>
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let ElementSize = ElementSizeNone;
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}
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multiclass sve_int_log_imm<bits<2> opc, string asm, string alias> {
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multiclass sve_int_log_imm<bits<2> opc, string asm, string alias, SDPatternOperator op> {
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def NAME : sve_int_log_imm<opc, asm>;
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def : SVE_1_Op_Imm_Log_Pat<nxv16i8, op, ZPR8, SVELogicalImm8Pat, !cast<Instruction>(NAME)>;
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def : SVE_1_Op_Imm_Log_Pat<nxv8i16, op, ZPR16, SVELogicalImm16Pat, !cast<Instruction>(NAME)>;
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def : SVE_1_Op_Imm_Log_Pat<nxv4i32, op, ZPR32, SVELogicalImm32Pat, !cast<Instruction>(NAME)>;
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def : SVE_1_Op_Imm_Log_Pat<nxv2i64, op, ZPR64, SVELogicalImm64Pat, !cast<Instruction>(NAME)>;
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def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
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(!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8:$imm), 4>;
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def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
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@ -0,0 +1,122 @@
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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define <vscale x 16 x i8> @orr_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: orr_i8:
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; CHECK: orr z0.b, z0.b, #0xf
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.imm.nxv16i8(<vscale x 16 x i8> %a,
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i64 15)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @orr_i16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: orr_i16:
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; CHECK: orr z0.h, z0.h, #0xfc07
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.imm.nxv8i16(<vscale x 8 x i16> %a,
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i64 64519)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @orr_i32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: orr_i32:
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; CHECK: orr z0.s, z0.s, #0xffff00
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.imm.nxv4i32(<vscale x 4 x i32> %a,
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i64 16776960)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @orr_i64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: orr_i64:
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; CHECK: orr z0.d, z0.d, #0xfffc000000000000
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.imm.nxv2i64(<vscale x 2 x i64> %a,
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i64 18445618173802708992)
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 16 x i8> @eor_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: eor_i8:
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; CHECK: eor z0.b, z0.b, #0xf
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.imm.nxv16i8(<vscale x 16 x i8> %a,
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i64 15)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @eor_i16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: eor_i16:
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; CHECK: eor z0.h, z0.h, #0xfc07
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.imm.nxv8i16(<vscale x 8 x i16> %a,
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i64 64519)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @eor_i32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: eor_i32:
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; CHECK: eor z0.s, z0.s, #0xffff00
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.imm.nxv4i32(<vscale x 4 x i32> %a,
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i64 16776960)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @eor_i64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: eor_i64:
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; CHECK: eor z0.d, z0.d, #0xfffc000000000000
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.imm.nxv2i64(<vscale x 2 x i64> %a,
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i64 18445618173802708992)
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: and_i8:
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; CHECK: and z0.b, z0.b, #0xf
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.aarch64.sve.and.imm.nxv16i8(<vscale x 16 x i8> %a,
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i64 15)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: and_i16:
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; CHECK: and z0.h, z0.h, #0xfc07
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.aarch64.sve.and.imm.nxv8i16(<vscale x 8 x i16> %a,
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i64 64519)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: and_i32:
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; CHECK: and z0.s, z0.s, #0xffff00
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.and.imm.nxv4i32(<vscale x 4 x i32> %a,
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i64 16776960)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: and_i64:
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; CHECK: and z0.d, z0.d, #0xfffc000000000000
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.and.imm.nxv2i64(<vscale x 2 x i64> %a,
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i64 18445618173802708992)
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ret <vscale x 2 x i64> %res
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.orr.imm.nxv16i8(<vscale x 16 x i8>, i64)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.orr.imm.nxv8i16(<vscale x 8 x i16>, i64)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.imm.nxv4i32(<vscale x 4 x i32>, i64)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.orr.imm.nxv2i64(<vscale x 2 x i64>, i64)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.eor.imm.nxv16i8(<vscale x 16 x i8>, i64)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.eor.imm.nxv8i16(<vscale x 8 x i16>, i64)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.imm.nxv4i32(<vscale x 4 x i32>, i64)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.eor.imm.nxv2i64(<vscale x 2 x i64>, i64)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.and.imm.nxv16i8(<vscale x 16 x i8>, i64)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.and.imm.nxv8i16(<vscale x 8 x i16>, i64)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.and.imm.nxv4i32(<vscale x 4 x i32>, i64)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.and.imm.nxv2i64(<vscale x 2 x i64>, i64)
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