From f9317bf0bed0e0f248c18114afa24dcd56d727ae Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Fri, 30 Sep 2022 16:44:07 -0700 Subject: [PATCH] Fix tied operands in phi-coalescing.mir test; try to adapt MLRegalloc tests Fix a test using invalid MLIR using different VRegs for the tied operands of ADD64rr, which happened to trigger an assertion after my latest changes. Also attempting to adjust the MLRegalloc tests to the adjusted regalloc (though I don't have a 100% working setup for them even without my changes) --- .../MLRegalloc/Inputs/reference-prio-log-noml.txt | 10 ---------- .../MLRegalloc/dev-mode-extra-features-logging.ll | 9 +++++---- llvm/test/CodeGen/MLRegalloc/dev-mode-logging.ll | 12 +++++++----- .../test/CodeGen/MLRegalloc/dev-mode-prio-logging.ll | 12 ++++++++---- llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir | 8 ++++---- 5 files changed, 24 insertions(+), 27 deletions(-) diff --git a/llvm/test/CodeGen/MLRegalloc/Inputs/reference-prio-log-noml.txt b/llvm/test/CodeGen/MLRegalloc/Inputs/reference-prio-log-noml.txt index 271480214546..719e330818dc 100644 --- a/llvm/test/CodeGen/MLRegalloc/Inputs/reference-prio-log-noml.txt +++ b/llvm/test/CodeGen/MLRegalloc/Inputs/reference-prio-log-noml.txt @@ -70,8 +70,6 @@ fields { feature { int64_list { value: 0 } } feature { int64_list { value: 0 } } feature { int64_list { value: 0 } } - feature { int64_list { value: 0 } } - feature { int64_list { value: 0 } } feature { int64_list { value: 0 } } } } feature_list { key: \"priority\" value { @@ -114,7 +112,6 @@ fields { feature { float_list { value: 2.68435763e+09 } } feature { float_list { value: 2.68435584e+09 } } feature { float_list { value: 2.14748365e+09 } } - feature { float_list { value: 3.75810074e+09 } } feature { float_list { value: 2.68435814e+09 } } feature { float_list { value: 3584 } } feature { float_list { value: 2.68435814e+09 } } @@ -131,7 +128,6 @@ fields { feature { float_list { value: 2.6843584e+09 } } feature { float_list { value: 3.75809664e+09 } } feature { float_list { value: 2.68435482e+09 } } - feature { float_list { value: 2.68435482e+09 } } feature { float_list { value: 2.68435814e+09 } } feature { float_list { value: 2.68435482e+09 } } feature { float_list { value: 2.68435456e+09 } } @@ -212,8 +208,6 @@ fields { feature { float_list { value: 0 } } feature { float_list { value: 0 } } feature { float_list { value: 0 } } - feature { float_list { value: 0 } } - feature { float_list { value: 0 } } feature { float_list { value: 36.6412773 } } } } feature_list { key: \"stage\" value { @@ -283,8 +277,6 @@ fields { feature { int64_list { value: 0 } } feature { int64_list { value: 0 } } feature { int64_list { value: 0 } } - feature { int64_list { value: 0 } } - feature { int64_list { value: 0 } } feature { int64_list { value: 0 } } } } feature_list { key: \"weight\" value { @@ -354,8 +346,6 @@ fields { feature { float_list { value: 0 } } feature { float_list { value: 0 } } feature { float_list { value: 0 } } - feature { float_list { value: 0 } } - feature { float_list { value: 0 } } feature { float_list { value: 0 } } } } } " } } diff --git a/llvm/test/CodeGen/MLRegalloc/dev-mode-extra-features-logging.ll b/llvm/test/CodeGen/MLRegalloc/dev-mode-extra-features-logging.ll index 7ab0115299cd..e8f7ee4c8c41 100644 --- a/llvm/test/CodeGen/MLRegalloc/dev-mode-extra-features-logging.ll +++ b/llvm/test/CodeGen/MLRegalloc/dev-mode-extra-features-logging.ll @@ -4,7 +4,8 @@ ; Check that we log the currently in development features correctly with both the default ; case and with a learned policy. ; -; RUN: llc -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-advisor=development \ +; RUN: llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy \ +; RUN: -regalloc-enable-advisor=development \ ; RUN: -regalloc-training-log=%t1 -tfutils-text-log \ ; RUN: -regalloc-enable-development-features < %S/Inputs/input.ll ; RUN: sed -i 's/ \+/ /g' %t1 @@ -16,7 +17,8 @@ ; RUN: rm -rf %t && mkdir %t ; RUN: %python %S/../../../lib/Analysis/models/gen-regalloc-eviction-test-model.py %t_savedmodel ; RUN: %python %S/../../../lib/Analysis/models/saved-model-to-tflite.py %t_savedmodel %t -; RUN: llc -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-advisor=development \ +; RUN: llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy \ +; RUN: -regalloc-enable-advisor=development \ ; RUN: -regalloc-training-log=%t2 -tfutils-text-log -regalloc-model=%t \ ; RUN: -regalloc-enable-development-features < %S/Inputs/input.ll ; RUN: sed -i 's/ \+/ /g' %t2 @@ -29,7 +31,6 @@ ; CHECK-LABEL: key: \"instructions\" ; Check the first five opcodes in the first eviction problem ; CHECK-NEXT: value: 19 -; CHECK-SAME: value: 19 ; CHECK-SAME: value: 3031 ; CHECK-SAME: value: 1245 ; CHECK-SAME: value: 1264 @@ -48,7 +49,7 @@ ; Ensure that we can still go through the mapping matrices for the rest of the ; eviction problems to make sure we haven't hit the end of the matrix above. ; There are a total of 23 eviction problems with this test. -; CHECK-COUNT-22: int64_list +; CHECK-COUNT-15: int64_list ; CHECK: key: \"is_free\" ; Make sure that we're exporting the mbb_frequencies. Don't actually check ; values due to all values being floating point/liable to change very easily. diff --git a/llvm/test/CodeGen/MLRegalloc/dev-mode-logging.ll b/llvm/test/CodeGen/MLRegalloc/dev-mode-logging.ll index e1a3dada665e..7d60125dcefb 100644 --- a/llvm/test/CodeGen/MLRegalloc/dev-mode-logging.ll +++ b/llvm/test/CodeGen/MLRegalloc/dev-mode-logging.ll @@ -3,8 +3,9 @@ ; ; Check that we log correctly, both with a learned policy, and the default policy ; -; RUN: llc -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-advisor=development \ -; RUN: -regalloc-training-log=%t1 -tfutils-text-log < %S/Inputs/input.ll +; RUN: llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy \ +; RUN: -regalloc-enable-advisor=development -regalloc-training-log=%t1 \ +; RUN: -tfutils-text-log < %S/Inputs/input.ll ; RUN: sed -i 's/ \+/ /g' %t1 ; RUN: sed -i 's/\\n key:/\n key:/g' %t1 ; RUN: sed -i 's/\\n feature/\n feature/g' %t1 @@ -15,8 +16,9 @@ ; RUN: rm -rf %t_savedmodel %t ; RUN: %python %S/../../../lib/Analysis/models/gen-regalloc-eviction-test-model.py %t_savedmodel ; RUN: %python %S/../../../lib/Analysis/models/saved-model-to-tflite.py %t_savedmodel %t -; RUN: llc -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-advisor=development \ -; RUN: -regalloc-training-log=%t2 -tfutils-text-log -regalloc-model=%t < %S/Inputs/input.ll +; RUN: llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy \ +; RUN: -regalloc-enable-advisor=development -regalloc-training-log=%t2 \ +; RUN: -tfutils-text-log -regalloc-model=%t < %S/Inputs/input.ll ; RUN: sed -i 's/ \+/ /g' %t2 ; RUN: sed -i 's/\\n key:/\n key:/g' %t2 ; RUN: sed -i 's/\\n feature/\n feature/g' %t2 @@ -27,7 +29,7 @@ ; CHECK-LABEL: key: \"index_to_evict\" ; CHECK-NEXT: value: 9 ; ML-NEXT: value: 9 -; NOML-NEXT: value: 32 +; NOML-NEXT: value: 12 ; CHECK-LABEL: key: \"reward\" ; ML: value: 36.90 ; NOML: value: 36.64 diff --git a/llvm/test/CodeGen/MLRegalloc/dev-mode-prio-logging.ll b/llvm/test/CodeGen/MLRegalloc/dev-mode-prio-logging.ll index 05f059c87cda..facaadbf85a5 100644 --- a/llvm/test/CodeGen/MLRegalloc/dev-mode-prio-logging.ll +++ b/llvm/test/CodeGen/MLRegalloc/dev-mode-prio-logging.ll @@ -3,8 +3,10 @@ ; ; Check that we log correctly, both with a learned policy, and the default policy ; -; RUN: llc -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-priority-advisor=development \ -; RUN: -regalloc-priority-training-log=%t1 -tfutils-text-log < %S/Inputs/input.ll +; RUN: llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy \ +; RUN: -regalloc-enable-priority-advisor=development \ +; RUN: -regalloc-priority-training-log=%t1 -tfutils-text-log \ +; RUN: < %S/Inputs/input.ll ; RUN: sed -i 's/ \+/ /g' %t1 ; RUN: sed -i 's/\\n key:/\n key:/g' %t1 ; RUN: sed -i 's/\\n feature/\n feature/g' %t1 @@ -15,8 +17,10 @@ ; RUN: rm -rf %t && mkdir %t ; RUN: %python %S/../../../lib/Analysis/models/gen-regalloc-priority-test-model.py %t_savedmodel ; RUN: %python %S/../../../lib/Analysis/models/saved-model-to-tflite.py %t_savedmodel %t -; RUN: llc -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-priority-advisor=development \ -; RUN: -regalloc-priority-training-log=%t2 -tfutils-text-log -regalloc-priority-model=%t < %S/Inputs/input.ll +; RUN: llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy \ +; RUN: -regalloc-enable-priority-advisor=development \ +; RUN: -regalloc-priority-training-log=%t2 -tfutils-text-log \ +; RUN: -regalloc-priority-model=%t < %S/Inputs/input.ll ; RUN: sed -i 's/ \+/ /g' %t2 ; RUN: sed -i 's/\\n key:/\n key:/g' %t2 ; RUN: sed -i 's/\\n feature/\n feature/g' %t2 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir index 9dd8a8ce2239..76eae532109e 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir @@ -138,7 +138,7 @@ body: | ; Verify that the vreg is different immediately after register coalescing. ; DOESCOALESCE-NOT: %10:gr64 ADD64ri32 - ; DOESCOALESCE: %{{[0-9]+}}:gr64 = ADD64ri32 + ; DOESCOALESCE: %{{[0-9]+}}:gr64_with_sub_8bit = ADD64ri32 ; Verify that all these registers land in r14. ; CHECK: renamable $r14 = ADD64ri32 killed renamable $r14 @@ -148,12 +148,12 @@ body: | %2:gr64 = PHI %9, %bb.0, %10, %bb.1, debug-instr-number 1, debug-location !13 ; CHECK: DBG_PHI $r14, 1 DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13 - %14:gr64 = ADD64rr killed %2, %6, implicit-def $eflags, debug-location !13 + %2:gr64 = ADD64rr killed %2, %6, implicit-def $eflags, debug-location !13 ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13 - $rdi = COPY %14, debug-location !13 + $rdi = COPY %2, debug-location !13 CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13 ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13 - %13:gr32 = COPY %14.sub_32bit, debug-location !13 + %13:gr32 = COPY %2.sub_32bit, debug-location !13 $eax = COPY %13, debug-location !13 RET64 implicit $eax, debug-location !13