forked from OSchip/llvm-project
Fix tied operands in phi-coalescing.mir test; try to adapt MLRegalloc tests
Fix a test using invalid MLIR using different VRegs for the tied operands of ADD64rr, which happened to trigger an assertion after my latest changes. Also attempting to adjust the MLRegalloc tests to the adjusted regalloc (though I don't have a 100% working setup for them even without my changes)
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@ -70,8 +70,6 @@ fields {
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feature { int64_list { value: 0 } }
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feature { int64_list { value: 0 } }
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feature { int64_list { value: 0 } }
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feature { int64_list { value: 0 } }
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feature { int64_list { value: 0 } }
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feature { int64_list { value: 0 } } } }
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feature_list {
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key: \"priority\" value {
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@ -114,7 +112,6 @@ fields {
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feature { float_list { value: 2.68435763e+09 } }
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feature { float_list { value: 2.68435584e+09 } }
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feature { float_list { value: 2.14748365e+09 } }
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feature { float_list { value: 3.75810074e+09 } }
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feature { float_list { value: 2.68435814e+09 } }
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feature { float_list { value: 3584 } }
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feature { float_list { value: 2.68435814e+09 } }
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@ -131,7 +128,6 @@ fields {
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feature { float_list { value: 2.6843584e+09 } }
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feature { float_list { value: 3.75809664e+09 } }
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feature { float_list { value: 2.68435482e+09 } }
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feature { float_list { value: 2.68435482e+09 } }
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feature { float_list { value: 2.68435814e+09 } }
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feature { float_list { value: 2.68435482e+09 } }
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feature { float_list { value: 2.68435456e+09 } }
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@ -212,8 +208,6 @@ fields {
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feature { float_list { value: 0 } }
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feature { float_list { value: 0 } }
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feature { float_list { value: 0 } }
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feature { float_list { value: 0 } }
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feature { float_list { value: 0 } }
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feature { float_list { value: 36.6412773 } } } }
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feature_list {
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key: \"stage\" value {
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@ -283,8 +277,6 @@ fields {
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feature { int64_list { value: 0 } }
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feature { int64_list { value: 0 } }
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feature { int64_list { value: 0 } }
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feature { int64_list { value: 0 } }
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feature { int64_list { value: 0 } }
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feature { int64_list { value: 0 } } } }
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feature_list {
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key: \"weight\" value {
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@ -354,8 +346,6 @@ fields {
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feature { float_list { value: 0 } }
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feature { float_list { value: 0 } }
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feature { float_list { value: 0 } }
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feature { float_list { value: 0 } }
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feature { float_list { value: 0 } }
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feature { float_list { value: 0 } } } } } "
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}
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}
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@ -4,7 +4,8 @@
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; Check that we log the currently in development features correctly with both the default
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; case and with a learned policy.
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;
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; RUN: llc -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-advisor=development \
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; RUN: llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy \
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; RUN: -regalloc-enable-advisor=development \
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; RUN: -regalloc-training-log=%t1 -tfutils-text-log \
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; RUN: -regalloc-enable-development-features < %S/Inputs/input.ll
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; RUN: sed -i 's/ \+/ /g' %t1
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@ -16,7 +17,8 @@
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; RUN: rm -rf %t && mkdir %t
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; RUN: %python %S/../../../lib/Analysis/models/gen-regalloc-eviction-test-model.py %t_savedmodel
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; RUN: %python %S/../../../lib/Analysis/models/saved-model-to-tflite.py %t_savedmodel %t
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; RUN: llc -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-advisor=development \
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; RUN: llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy \
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; RUN: -regalloc-enable-advisor=development \
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; RUN: -regalloc-training-log=%t2 -tfutils-text-log -regalloc-model=%t \
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; RUN: -regalloc-enable-development-features < %S/Inputs/input.ll
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; RUN: sed -i 's/ \+/ /g' %t2
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@ -29,7 +31,6 @@
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; CHECK-LABEL: key: \"instructions\"
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; Check the first five opcodes in the first eviction problem
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; CHECK-NEXT: value: 19
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; CHECK-SAME: value: 19
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; CHECK-SAME: value: 3031
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; CHECK-SAME: value: 1245
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; CHECK-SAME: value: 1264
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@ -48,7 +49,7 @@
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; Ensure that we can still go through the mapping matrices for the rest of the
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; eviction problems to make sure we haven't hit the end of the matrix above.
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; There are a total of 23 eviction problems with this test.
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; CHECK-COUNT-22: int64_list
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; CHECK-COUNT-15: int64_list
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; CHECK: key: \"is_free\"
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; Make sure that we're exporting the mbb_frequencies. Don't actually check
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; values due to all values being floating point/liable to change very easily.
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@ -3,8 +3,9 @@
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;
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; Check that we log correctly, both with a learned policy, and the default policy
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;
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; RUN: llc -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-advisor=development \
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; RUN: -regalloc-training-log=%t1 -tfutils-text-log < %S/Inputs/input.ll
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; RUN: llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy \
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; RUN: -regalloc-enable-advisor=development -regalloc-training-log=%t1 \
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; RUN: -tfutils-text-log < %S/Inputs/input.ll
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; RUN: sed -i 's/ \+/ /g' %t1
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; RUN: sed -i 's/\\n key:/\n key:/g' %t1
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; RUN: sed -i 's/\\n feature/\n feature/g' %t1
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@ -15,8 +16,9 @@
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; RUN: rm -rf %t_savedmodel %t
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; RUN: %python %S/../../../lib/Analysis/models/gen-regalloc-eviction-test-model.py %t_savedmodel
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; RUN: %python %S/../../../lib/Analysis/models/saved-model-to-tflite.py %t_savedmodel %t
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; RUN: llc -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-advisor=development \
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; RUN: -regalloc-training-log=%t2 -tfutils-text-log -regalloc-model=%t < %S/Inputs/input.ll
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; RUN: llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy \
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; RUN: -regalloc-enable-advisor=development -regalloc-training-log=%t2 \
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; RUN: -tfutils-text-log -regalloc-model=%t < %S/Inputs/input.ll
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; RUN: sed -i 's/ \+/ /g' %t2
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; RUN: sed -i 's/\\n key:/\n key:/g' %t2
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; RUN: sed -i 's/\\n feature/\n feature/g' %t2
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@ -27,7 +29,7 @@
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; CHECK-LABEL: key: \"index_to_evict\"
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; CHECK-NEXT: value: 9
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; ML-NEXT: value: 9
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; NOML-NEXT: value: 32
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; NOML-NEXT: value: 12
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; CHECK-LABEL: key: \"reward\"
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; ML: value: 36.90
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; NOML: value: 36.64
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@ -3,8 +3,10 @@
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;
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; Check that we log correctly, both with a learned policy, and the default policy
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;
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; RUN: llc -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-priority-advisor=development \
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; RUN: -regalloc-priority-training-log=%t1 -tfutils-text-log < %S/Inputs/input.ll
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; RUN: llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy \
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; RUN: -regalloc-enable-priority-advisor=development \
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; RUN: -regalloc-priority-training-log=%t1 -tfutils-text-log \
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; RUN: < %S/Inputs/input.ll
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; RUN: sed -i 's/ \+/ /g' %t1
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; RUN: sed -i 's/\\n key:/\n key:/g' %t1
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; RUN: sed -i 's/\\n feature/\n feature/g' %t1
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@ -15,8 +17,10 @@
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; RUN: rm -rf %t && mkdir %t
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; RUN: %python %S/../../../lib/Analysis/models/gen-regalloc-priority-test-model.py %t_savedmodel
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; RUN: %python %S/../../../lib/Analysis/models/saved-model-to-tflite.py %t_savedmodel %t
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; RUN: llc -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-priority-advisor=development \
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; RUN: -regalloc-priority-training-log=%t2 -tfutils-text-log -regalloc-priority-model=%t < %S/Inputs/input.ll
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; RUN: llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy \
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; RUN: -regalloc-enable-priority-advisor=development \
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; RUN: -regalloc-priority-training-log=%t2 -tfutils-text-log \
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; RUN: -regalloc-priority-model=%t < %S/Inputs/input.ll
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; RUN: sed -i 's/ \+/ /g' %t2
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; RUN: sed -i 's/\\n key:/\n key:/g' %t2
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; RUN: sed -i 's/\\n feature/\n feature/g' %t2
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@ -138,7 +138,7 @@ body: |
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; Verify that the vreg is different immediately after register coalescing.
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; DOESCOALESCE-NOT: %10:gr64 ADD64ri32
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; DOESCOALESCE: %{{[0-9]+}}:gr64 = ADD64ri32
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; DOESCOALESCE: %{{[0-9]+}}:gr64_with_sub_8bit = ADD64ri32
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; Verify that all these registers land in r14.
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; CHECK: renamable $r14 = ADD64ri32 killed renamable $r14
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%2:gr64 = PHI %9, %bb.0, %10, %bb.1, debug-instr-number 1, debug-location !13
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; CHECK: DBG_PHI $r14, 1
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DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
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%14:gr64 = ADD64rr killed %2, %6, implicit-def $eflags, debug-location !13
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%2:gr64 = ADD64rr killed %2, %6, implicit-def $eflags, debug-location !13
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ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
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$rdi = COPY %14, debug-location !13
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$rdi = COPY %2, debug-location !13
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CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13
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ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
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%13:gr32 = COPY %14.sub_32bit, debug-location !13
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%13:gr32 = COPY %2.sub_32bit, debug-location !13
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$eax = COPY %13, debug-location !13
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RET64 implicit $eax, debug-location !13
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