forked from OSchip/llvm-project
Convert the XForm instrs and XSForm instruction over to use isDOT
llvm-svn: 21351
This commit is contained in:
Chris Lattner
parent
5b78da4571
commit
f9172e14c9
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@ -194,51 +194,55 @@ class DSForm_2<bits<6> opcode, bits<2> xo, dag OL, string asmstr>
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: DSForm_1<opcode, xo, OL, asmstr>;
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// 1.7.6 X-Form
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class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc,
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class XForm_base_r3xo<bits<6> opcode, bits<10> xo,
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dag OL, string asmstr> : I<opcode, OL, asmstr> {
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bits<5> RST;
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bits<5> A;
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bits<5> B;
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bit RC = 0; // set by isDOT
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let Inst{6-10} = RST;
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let Inst{11-15} = A;
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let Inst{16-20} = B;
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let Inst{21-30} = xo;
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let Inst{31} = rc;
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let Inst{31} = RC;
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}
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// This is the same as XForm_base_r3xo, but the first two operands are swapped
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// when code is emitted.
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class XForm_base_r3xo_swapped
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<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
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<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: I<opcode, OL, asmstr> {
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bits<5> A;
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bits<5> RST;
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bits<5> B;
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bit RC = 0; // set by isDOT
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let Inst{6-10} = RST;
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let Inst{11-15} = A;
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let Inst{16-20} = B;
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let Inst{21-30} = xo;
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let Inst{31} = rc;
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let Inst{31} = RC;
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}
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class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, 0, OL, asmstr>;
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: XForm_base_r3xo<opcode, xo, OL, asmstr>;
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class XForm_6<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, rc, OL, asmstr>;
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class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, OL, asmstr>;
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class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, 0, OL, asmstr>;
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: XForm_base_r3xo<opcode, xo, OL, asmstr>;
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class XForm_10<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, rc, OL, asmstr> {
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class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> {
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}
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class XForm_11<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, rc, OL, asmstr> {
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class XForm_11<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> {
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let B = 0;
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}
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@ -278,16 +282,16 @@ class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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}
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class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, 0, OL, asmstr> {
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: XForm_base_r3xo<opcode, xo, OL, asmstr> {
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}
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class XForm_26<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, rc, OL, asmstr> {
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class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, OL, asmstr> {
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let A = 0;
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}
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class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, 0, OL, asmstr> {
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: XForm_base_r3xo<opcode, xo, OL, asmstr> {
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}
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// 1.7.7 XL-Form
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@ -397,18 +401,20 @@ class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
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}
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// 1.7.10 XS-Form
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class XSForm_1<bits<6> opcode, bits<9> xo, bit rc, dag OL, string asmstr>
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class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr>
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: I<opcode, OL, asmstr> {
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bits<5> RS;
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bits<5> A;
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bits<6> SH;
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bit RC = 0; // set by isDOT
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let Inst{6-10} = RS;
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let Inst{11-15} = A;
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let Inst{16-20} = SH{1-5};
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let Inst{21-29} = xo;
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let Inst{30} = SH{0};
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let Inst{31} = rc;
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let Inst{31} = RC;
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}
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// 1.7.11 XO-Form
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@ -17,6 +17,10 @@ include "PowerPCInstrFormats.td"
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class isPPC64 { bit PPC64 = 1; }
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class isVMX { bit VMX = 1; }
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class isDOT {
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list<Register> Defs = [CR0];
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bit RC = 1;
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}
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let isTerminator = 1 in {
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let isReturn = 1 in
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@ -218,39 +222,37 @@ def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"ldx $dst, $base, $index">, isPPC64;
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}
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def AND : XForm_6<31, 28, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"and $rA, $rS, $rB">;
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let Defs = [CR0] in
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def ANDo : XForm_6<31, 28, 1, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"and. $rA, $rS, $rB">;
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def ANDC : XForm_6<31, 60, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"and. $rA, $rS, $rB">, isDOT;
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def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"andc $rA, $rS, $rB">;
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def EQV : XForm_6<31, 284, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"eqv $rA, $rS, $rB">;
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def NAND : XForm_6<31, 476, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"nand $rA, $rS, $rB">;
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def NOR : XForm_6<31, 124, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"nor $rA, $rS, $rB">;
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def OR : XForm_6<31, 444, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"or $rA, $rS, $rB">;
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let Defs = [CR0] in
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def ORo : XForm_6<31, 444, 1, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"or. $rA, $rS, $rB">;
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def ORC : XForm_6<31, 412, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"or. $rA, $rS, $rB">, isDOT;
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def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"orc $rA, $rS, $rB">;
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def SLD : XForm_6<31, 27, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"sld $rA, $rS, $rB">, isPPC64;
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def SLW : XForm_6<31, 24, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"slw $rA, $rS, $rB">;
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def SRD : XForm_6<31, 539, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srd $rA, $rS, $rB">, isPPC64;
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def SRW : XForm_6<31, 536, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srw $rA, $rS, $rB">;
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def SRAD : XForm_6<31, 794, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srad $rA, $rS, $rB">, isPPC64;
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def SRAW : XForm_6<31, 792, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"sraw $rA, $rS, $rB">;
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def XOR : XForm_6<31, 316, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"xor $rA, $rS, $rB">;
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let isStore = 1 in {
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def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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@ -266,15 +268,15 @@ def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdux $rS, $rA, $rB">, isPPC64;
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}
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def SRAWI : XForm_10<31, 824, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
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def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
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"srawi $rA, $rS, $SH">;
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def CNTLZW : XForm_11<31, 26, 0, (ops GPRC:$rA, GPRC:$rS),
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def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
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"cntlzw $rA, $rS">;
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def EXTSB : XForm_11<31, 954, 0, (ops GPRC:$rA, GPRC:$rS),
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def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
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"extsb $rA, $rS">;
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def EXTSH : XForm_11<31, 922, 0, (ops GPRC:$rA, GPRC:$rS),
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def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
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"extsh $rA, $rS">;
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def EXTSW : XForm_11<31, 986, 0, (ops GPRC:$rA, GPRC:$rS),
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def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
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"extsw $rA, $rS">, isPPC64;
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def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
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"cmp $crD, $long, $rA, $rB">;
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@ -298,21 +300,21 @@ def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
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def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
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"lfdx $dst, $base, $index">;
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}
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def FCFID : XForm_26<63, 846, 0, (ops FPRC:$frD, FPRC:$frB),
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def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
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"fcfid $frD, $frB">, isPPC64;
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def FCTIDZ : XForm_26<63, 815, 0, (ops FPRC:$frD, FPRC:$frB),
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def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
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"fctidz $frD, $frB">, isPPC64;
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def FCTIWZ : XForm_26<63, 15, 0, (ops FPRC:$frD, FPRC:$frB),
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def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
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"fctiwz $frD, $frB">;
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def FABS : XForm_26<63, 264, 0, (ops FPRC:$frD, FPRC:$frB),
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def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
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"fabs $frD, $frB">;
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def FMR : XForm_26<63, 72, 0, (ops FPRC:$frD, FPRC:$frB),
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def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
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"fmr $frD, $frB">;
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def FNABS : XForm_26<63, 136, 0, (ops FPRC:$frD, FPRC:$frB),
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def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
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"fnabs $frD, $frB">;
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def FNEG : XForm_26<63, 40, 0, (ops FPRC:$frD, FPRC:$frB),
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def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
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"fneg $frD, $frB">;
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def FRSP : XForm_26<63, 12, 0, (ops FPRC:$frD, FPRC:$frB),
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def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
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"frsp $frD, $frB">;
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let isStore = 1 in {
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def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
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@ -367,7 +369,7 @@ def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
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// XS-Form instructions. Just 'sradi'
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//
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def SRADI : XSForm_1<31, 413, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
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def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
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"sradi $rA, $rS, $SH">, isPPC64;
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// XO-Form instructions. Arithmetic instructions that can set overflow bit
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