forked from OSchip/llvm-project
[AArch64][SME] Add SME outer product intrinsics
This patch adds the following intrinsics to support the SME ACLE: * @llvm.aarch64.sme.mopa: Non-widening outer product + accumulate * @llvm.aarch64.sme.mops: Non-widening outer product + subtract * @llvm.aarch64.sme.mopa.wide: Widening outer product + accumulate * @llvm.aarch64.sme.mops.wide: Widening outer product + subtract * @llvm.aarch64.sme.smopa.wide: Widening signed sum of outer product + accumulate * @llvm.aarch64.sme.smops.wide: Widening signed sum of outer product + subtract * @llvm.aarch64.sme.umopa.wide: Widening unsigned sum of outer product + accumulate * @llvm.aarch64.sme.umops.wide: Widening unsigned sum of outer product + subtract * @llvm.aarch64.sme.sumopa.wide: Widening signed by unsigned sum of outer product + accumulate * @llvm.aarch64.sme.sumops.wide: Widening signed by unsigned sum of outer product + subtract * @llvm.aarch64.sme.usmopa.wide: Widening unsigned by signed sum of outer product + accumulate * @llvm.aarch64.sme.usmops.wide: Widening unsigned by signed sum of outer product + subtract Differential Revision: https://reviews.llvm.org/D127956
This commit is contained in:
David Sherwood
parent
5548e807b5
commit
f916ee0fb1
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@ -2652,6 +2652,29 @@ let TargetPrefix = "aarch64" in {
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def int_aarch64_sme_zero : DefaultAttrsIntrinsic<[], [llvm_i64_ty]>;
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class SME_OuterProduct_Intrinsic
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: DefaultAttrsIntrinsic<[],
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[llvm_i64_ty,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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LLVMMatchType<0>,
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llvm_anyvector_ty]>;
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def int_aarch64_sme_mopa : SME_OuterProduct_Intrinsic;
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def int_aarch64_sme_mops : SME_OuterProduct_Intrinsic;
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def int_aarch64_sme_mopa_wide : SME_OuterProduct_Intrinsic;
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def int_aarch64_sme_mops_wide : SME_OuterProduct_Intrinsic;
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def int_aarch64_sme_smopa_wide : SME_OuterProduct_Intrinsic;
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def int_aarch64_sme_smops_wide : SME_OuterProduct_Intrinsic;
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def int_aarch64_sme_umopa_wide : SME_OuterProduct_Intrinsic;
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def int_aarch64_sme_umops_wide : SME_OuterProduct_Intrinsic;
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def int_aarch64_sme_sumopa_wide : SME_OuterProduct_Intrinsic;
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def int_aarch64_sme_sumops_wide : SME_OuterProduct_Intrinsic;
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def int_aarch64_sme_usmopa_wide : SME_OuterProduct_Intrinsic;
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def int_aarch64_sme_usmops_wide : SME_OuterProduct_Intrinsic;
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//
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// Counting elements
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//
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@ -2372,6 +2372,23 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const {
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return BB;
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}
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MachineBasicBlock *
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AArch64TargetLowering::EmitMopa(unsigned Opc, unsigned BaseReg,
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MachineInstr &MI, MachineBasicBlock *BB) const {
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const TargetInstrInfo *TII = Subtarget->getInstrInfo();
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MachineInstrBuilder MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Opc));
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MIB.addReg(BaseReg + MI.getOperand(0).getImm(), RegState::Define);
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MIB.addReg(BaseReg + MI.getOperand(0).getImm());
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MIB.add(MI.getOperand(1)); // pn
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MIB.add(MI.getOperand(2)); // pm
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MIB.add(MI.getOperand(3)); // zn
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MIB.add(MI.getOperand(4)); // zm
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MI.eraseFromParent(); // The pseudo is gone now.
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return BB;
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}
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MachineBasicBlock *
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AArch64TargetLowering::EmitInsertVectorToTile(unsigned Opc, unsigned BaseReg,
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MachineInstr &MI,
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@ -2459,6 +2476,54 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
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return EmitTileLoad(AArch64::LD1_MXIPXX_V_Q, AArch64::ZAQ0, MI, BB);
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case AArch64::LDR_ZA_PSEUDO:
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return EmitFill(MI, BB);
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case AArch64::BFMOPA_MPPZZ_PSEUDO:
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return EmitMopa(AArch64::BFMOPA_MPPZZ, AArch64::ZAS0, MI, BB);
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case AArch64::BFMOPS_MPPZZ_PSEUDO:
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return EmitMopa(AArch64::BFMOPS_MPPZZ, AArch64::ZAS0, MI, BB);
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case AArch64::FMOPAL_MPPZZ_PSEUDO:
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return EmitMopa(AArch64::FMOPAL_MPPZZ, AArch64::ZAS0, MI, BB);
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case AArch64::FMOPSL_MPPZZ_PSEUDO:
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return EmitMopa(AArch64::FMOPSL_MPPZZ, AArch64::ZAS0, MI, BB);
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case AArch64::FMOPA_MPPZZ_S_PSEUDO:
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return EmitMopa(AArch64::FMOPA_MPPZZ_S, AArch64::ZAS0, MI, BB);
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case AArch64::FMOPS_MPPZZ_S_PSEUDO:
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return EmitMopa(AArch64::FMOPS_MPPZZ_S, AArch64::ZAS0, MI, BB);
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case AArch64::FMOPA_MPPZZ_D_PSEUDO:
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return EmitMopa(AArch64::FMOPA_MPPZZ_D, AArch64::ZAD0, MI, BB);
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case AArch64::FMOPS_MPPZZ_D_PSEUDO:
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return EmitMopa(AArch64::FMOPS_MPPZZ_D, AArch64::ZAD0, MI, BB);
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case AArch64::SMOPA_MPPZZ_S_PSEUDO:
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return EmitMopa(AArch64::SMOPA_MPPZZ_S, AArch64::ZAS0, MI, BB);
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case AArch64::SMOPS_MPPZZ_S_PSEUDO:
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return EmitMopa(AArch64::SMOPS_MPPZZ_S, AArch64::ZAS0, MI, BB);
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case AArch64::UMOPA_MPPZZ_S_PSEUDO:
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return EmitMopa(AArch64::UMOPA_MPPZZ_S, AArch64::ZAS0, MI, BB);
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case AArch64::UMOPS_MPPZZ_S_PSEUDO:
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return EmitMopa(AArch64::UMOPS_MPPZZ_S, AArch64::ZAS0, MI, BB);
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case AArch64::SUMOPA_MPPZZ_S_PSEUDO:
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return EmitMopa(AArch64::SUMOPA_MPPZZ_S, AArch64::ZAS0, MI, BB);
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case AArch64::SUMOPS_MPPZZ_S_PSEUDO:
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return EmitMopa(AArch64::SUMOPS_MPPZZ_S, AArch64::ZAS0, MI, BB);
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case AArch64::USMOPA_MPPZZ_S_PSEUDO:
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return EmitMopa(AArch64::USMOPA_MPPZZ_S, AArch64::ZAS0, MI, BB);
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case AArch64::USMOPS_MPPZZ_S_PSEUDO:
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return EmitMopa(AArch64::USMOPS_MPPZZ_S, AArch64::ZAS0, MI, BB);
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case AArch64::SMOPA_MPPZZ_D_PSEUDO:
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return EmitMopa(AArch64::SMOPA_MPPZZ_D, AArch64::ZAD0, MI, BB);
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case AArch64::SMOPS_MPPZZ_D_PSEUDO:
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return EmitMopa(AArch64::SMOPS_MPPZZ_D, AArch64::ZAD0, MI, BB);
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case AArch64::UMOPA_MPPZZ_D_PSEUDO:
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return EmitMopa(AArch64::UMOPA_MPPZZ_D, AArch64::ZAD0, MI, BB);
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case AArch64::UMOPS_MPPZZ_D_PSEUDO:
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return EmitMopa(AArch64::UMOPS_MPPZZ_D, AArch64::ZAD0, MI, BB);
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case AArch64::SUMOPA_MPPZZ_D_PSEUDO:
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return EmitMopa(AArch64::SUMOPA_MPPZZ_D, AArch64::ZAD0, MI, BB);
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case AArch64::SUMOPS_MPPZZ_D_PSEUDO:
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return EmitMopa(AArch64::SUMOPS_MPPZZ_D, AArch64::ZAD0, MI, BB);
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case AArch64::USMOPA_MPPZZ_D_PSEUDO:
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return EmitMopa(AArch64::USMOPA_MPPZZ_D, AArch64::ZAD0, MI, BB);
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case AArch64::USMOPS_MPPZZ_D_PSEUDO:
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return EmitMopa(AArch64::USMOPS_MPPZZ_D, AArch64::ZAD0, MI, BB);
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case AArch64::INSERT_MXIPZ_H_PSEUDO_B:
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return EmitInsertVectorToTile(AArch64::INSERT_MXIPZ_H_B, AArch64::ZAB0, MI,
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BB);
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@ -563,7 +563,8 @@ public:
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MachineInstr &MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitMopa(unsigned Opc, unsigned BaseReg, MachineInstr &MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitInsertVectorToTile(unsigned Opc, unsigned BaseReg,
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MachineInstr &MI,
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MachineBasicBlock *BB) const;
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@ -38,41 +38,41 @@ let Predicates = [HasSME] in {
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// Outer products
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//===----------------------------------------------------------------------===//
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defm BFMOPA_MPPZZ : sme_bf16_outer_product<0b0, "bfmopa">;
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defm BFMOPS_MPPZZ : sme_bf16_outer_product<0b1, "bfmops">;
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defm BFMOPA_MPPZZ : sme_bf16_outer_product<0b0, "bfmopa", int_aarch64_sme_mopa_wide>;
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defm BFMOPS_MPPZZ : sme_bf16_outer_product<0b1, "bfmops", int_aarch64_sme_mops_wide>;
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def FMOPA_MPPZZ_S : sme_outer_product_fp32<0b0, "fmopa">;
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def FMOPS_MPPZZ_S : sme_outer_product_fp32<0b1, "fmops">;
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defm FMOPA_MPPZZ_S : sme_outer_product_fp32<0b0, "fmopa", int_aarch64_sme_mopa>;
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defm FMOPS_MPPZZ_S : sme_outer_product_fp32<0b1, "fmops", int_aarch64_sme_mops>;
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}
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let Predicates = [HasSMEF64] in {
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def FMOPA_MPPZZ_D : sme_outer_product_fp64<0b0, "fmopa">;
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def FMOPS_MPPZZ_D : sme_outer_product_fp64<0b1, "fmops">;
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defm FMOPA_MPPZZ_D : sme_outer_product_fp64<0b0, "fmopa", int_aarch64_sme_mopa>;
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defm FMOPS_MPPZZ_D : sme_outer_product_fp64<0b1, "fmops", int_aarch64_sme_mops>;
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}
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let Predicates = [HasSME] in {
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defm FMOPAL_MPPZZ : sme_f16_outer_product<0b0, "fmopa">;
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defm FMOPSL_MPPZZ : sme_f16_outer_product<0b1, "fmops">;
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defm FMOPAL_MPPZZ : sme_f16_outer_product<0b0, "fmopa", int_aarch64_sme_mopa_wide>;
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defm FMOPSL_MPPZZ : sme_f16_outer_product<0b1, "fmops", int_aarch64_sme_mops_wide>;
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def SMOPA_MPPZZ_S : sme_int_outer_product_i32<0b000, "smopa">;
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def SMOPS_MPPZZ_S : sme_int_outer_product_i32<0b001, "smops">;
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def UMOPA_MPPZZ_S : sme_int_outer_product_i32<0b110, "umopa">;
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def UMOPS_MPPZZ_S : sme_int_outer_product_i32<0b111, "umops">;
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def SUMOPA_MPPZZ_S : sme_int_outer_product_i32<0b010, "sumopa">;
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def SUMOPS_MPPZZ_S : sme_int_outer_product_i32<0b011, "sumops">;
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def USMOPA_MPPZZ_S : sme_int_outer_product_i32<0b100, "usmopa">;
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def USMOPS_MPPZZ_S : sme_int_outer_product_i32<0b101, "usmops">;
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defm SMOPA_MPPZZ_S : sme_int_outer_product_i32<0b000, "smopa", int_aarch64_sme_smopa_wide>;
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defm SMOPS_MPPZZ_S : sme_int_outer_product_i32<0b001, "smops", int_aarch64_sme_smops_wide>;
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defm UMOPA_MPPZZ_S : sme_int_outer_product_i32<0b110, "umopa", int_aarch64_sme_umopa_wide>;
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defm UMOPS_MPPZZ_S : sme_int_outer_product_i32<0b111, "umops", int_aarch64_sme_umops_wide>;
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defm SUMOPA_MPPZZ_S : sme_int_outer_product_i32<0b010, "sumopa", int_aarch64_sme_sumopa_wide>;
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defm SUMOPS_MPPZZ_S : sme_int_outer_product_i32<0b011, "sumops", int_aarch64_sme_sumops_wide>;
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defm USMOPA_MPPZZ_S : sme_int_outer_product_i32<0b100, "usmopa", int_aarch64_sme_usmopa_wide>;
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defm USMOPS_MPPZZ_S : sme_int_outer_product_i32<0b101, "usmops", int_aarch64_sme_usmops_wide>;
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}
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let Predicates = [HasSMEI64] in {
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def SMOPA_MPPZZ_D : sme_int_outer_product_i64<0b000, "smopa">;
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def SMOPS_MPPZZ_D : sme_int_outer_product_i64<0b001, "smops">;
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def UMOPA_MPPZZ_D : sme_int_outer_product_i64<0b110, "umopa">;
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def UMOPS_MPPZZ_D : sme_int_outer_product_i64<0b111, "umops">;
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def SUMOPA_MPPZZ_D : sme_int_outer_product_i64<0b010, "sumopa">;
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def SUMOPS_MPPZZ_D : sme_int_outer_product_i64<0b011, "sumops">;
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def USMOPA_MPPZZ_D : sme_int_outer_product_i64<0b100, "usmopa">;
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def USMOPS_MPPZZ_D : sme_int_outer_product_i64<0b101, "usmops">;
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defm SMOPA_MPPZZ_D : sme_int_outer_product_i64<0b000, "smopa", int_aarch64_sme_smopa_wide>;
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defm SMOPS_MPPZZ_D : sme_int_outer_product_i64<0b001, "smops", int_aarch64_sme_smops_wide>;
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defm UMOPA_MPPZZ_D : sme_int_outer_product_i64<0b110, "umopa", int_aarch64_sme_umopa_wide>;
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defm UMOPS_MPPZZ_D : sme_int_outer_product_i64<0b111, "umops", int_aarch64_sme_umops_wide>;
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defm SUMOPA_MPPZZ_D : sme_int_outer_product_i64<0b010, "sumopa", int_aarch64_sme_sumopa_wide>;
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defm SUMOPS_MPPZZ_D : sme_int_outer_product_i64<0b011, "sumops", int_aarch64_sme_sumops_wide>;
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defm USMOPA_MPPZZ_D : sme_int_outer_product_i64<0b100, "usmopa", int_aarch64_sme_usmopa_wide>;
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defm USMOPS_MPPZZ_D : sme_int_outer_product_i64<0b101, "usmops", int_aarch64_sme_usmops_wide>;
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}
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let Predicates = [HasSME] in {
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@ -25,7 +25,8 @@ def TSV110Model : SchedMachineModel {
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let CompleteModel = 1;
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list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
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PAUnsupported.F);
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PAUnsupported.F,
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SMEUnsupported.F);
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}
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// Define each kind of processor resource and number available on the TSV110,
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@ -28,6 +28,14 @@ def am_sme_indexed_b4 :ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<0,15>",
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// SME Outer Products
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//===----------------------------------------------------------------------===//
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class sme_outer_product_pseudo<ZPRRegOp zpr_ty>
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: Pseudo<(outs), (ins i64imm:$tile, PPR3bAny:$pn, PPR3bAny:$pm,
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zpr_ty:$zn, zpr_ty:$zm), []>,
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Sched<[]> {
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// Translated to the actual instructions in AArch64ISelLowering.cpp
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let usesCustomInserter = 1;
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}
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class sme_fp_outer_product_inst<bit S, bit sz, MatrixTileOperand za_ty,
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ZPRRegOp zpr_ty, string mnemonic>
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: I<(outs za_ty:$ZAda),
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@ -52,17 +60,31 @@ class sme_fp_outer_product_inst<bit S, bit sz, MatrixTileOperand za_ty,
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let Constraints = "$ZAda = $_ZAda";
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}
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class sme_outer_product_fp32<bit S, string mnemonic>
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: sme_fp_outer_product_inst<S, 0b0, TileOp32, ZPR32, mnemonic> {
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bits<2> ZAda;
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let Inst{1-0} = ZAda;
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let Inst{2} = 0b0;
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multiclass sme_outer_product_fp32<bit S, string mnemonic, SDPatternOperator op> {
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def NAME : sme_fp_outer_product_inst<S, 0b0, TileOp32, ZPR32, mnemonic> {
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bits<2> ZAda;
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let Inst{1-0} = ZAda;
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let Inst{2} = 0b0;
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}
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def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR32>;
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def : Pat<(op imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm),
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(nxv4f32 ZPR32:$zn), (nxv4f32 ZPR32:$zm)),
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(!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
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}
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class sme_outer_product_fp64<bit S, string mnemonic>
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: sme_fp_outer_product_inst<S, 0b1, TileOp64, ZPR64, mnemonic> {
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bits<3> ZAda;
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let Inst{2-0} = ZAda;
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multiclass sme_outer_product_fp64<bit S, string mnemonic, SDPatternOperator op> {
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def NAME : sme_fp_outer_product_inst<S, 0b1, TileOp64, ZPR64, mnemonic> {
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bits<3> ZAda;
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let Inst{2-0} = ZAda;
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}
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def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR64>;
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def : Pat<(op imm0_7:$tile, (nxv2i1 PPR3bAny:$pn), (nxv2i1 PPR3bAny:$pm),
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(nxv2f64 ZPR64:$zn), (nxv2f64 ZPR64:$zm)),
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(!cast<Instruction>(NAME # _PSEUDO) imm0_7:$tile, $pn, $pm, $zn, $zm)>;
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}
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class sme_int_outer_product_inst<bit u0, bit u1, bit S, bit sz,
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@ -92,19 +114,35 @@ class sme_int_outer_product_inst<bit u0, bit u1, bit S, bit sz,
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let Constraints = "$ZAda = $_ZAda";
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}
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class sme_int_outer_product_i32<bits<3> opc, string mnemonic>
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: sme_int_outer_product_inst<opc{2}, opc{1}, opc{0}, 0b0, TileOp32, ZPR8,
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mnemonic> {
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bits<2> ZAda;
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let Inst{1-0} = ZAda;
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let Inst{2} = 0b0;
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multiclass sme_int_outer_product_i32<bits<3> opc, string mnemonic,
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SDPatternOperator op> {
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def NAME : sme_int_outer_product_inst<opc{2}, opc{1}, opc{0}, 0b0, TileOp32,
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ZPR8, mnemonic> {
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bits<2> ZAda;
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let Inst{1-0} = ZAda;
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let Inst{2} = 0b0;
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}
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def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR8>;
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|
||||
def : Pat<(op imm0_3:$tile, (nxv16i1 PPR3bAny:$pn), (nxv16i1 PPR3bAny:$pm),
|
||||
(nxv16i8 ZPR8:$zn), (nxv16i8 ZPR8:$zm)),
|
||||
(!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
|
||||
}
|
||||
|
||||
class sme_int_outer_product_i64<bits<3> opc, string mnemonic>
|
||||
: sme_int_outer_product_inst<opc{2}, opc{1}, opc{0}, 0b1, TileOp64, ZPR16,
|
||||
mnemonic> {
|
||||
bits<3> ZAda;
|
||||
let Inst{2-0} = ZAda;
|
||||
multiclass sme_int_outer_product_i64<bits<3> opc, string mnemonic,
|
||||
SDPatternOperator op> {
|
||||
def NAME : sme_int_outer_product_inst<opc{2}, opc{1}, opc{0}, 0b1, TileOp64,
|
||||
ZPR16, mnemonic> {
|
||||
bits<3> ZAda;
|
||||
let Inst{2-0} = ZAda;
|
||||
}
|
||||
|
||||
def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR16>;
|
||||
|
||||
def : Pat<(op imm0_7:$tile, (nxv8i1 PPR3bAny:$pn), (nxv8i1 PPR3bAny:$pm),
|
||||
(nxv8i16 ZPR16:$zn), (nxv8i16 ZPR16:$zm)),
|
||||
(!cast<Instruction>(NAME # _PSEUDO) imm0_7:$tile, $pn, $pm, $zn, $zm)>;
|
||||
}
|
||||
|
||||
class sme_outer_product_widening_inst<bit op, bit S, string mnemonic>
|
||||
|
|
@ -131,12 +169,24 @@ class sme_outer_product_widening_inst<bit op, bit S, string mnemonic>
|
|||
let Constraints = "$ZAda = $_ZAda";
|
||||
}
|
||||
|
||||
multiclass sme_bf16_outer_product<bit S, string mnemonic> {
|
||||
def : sme_outer_product_widening_inst<0b0, S, mnemonic>;
|
||||
multiclass sme_bf16_outer_product<bit S, string mnemonic, SDPatternOperator op> {
|
||||
def NAME : sme_outer_product_widening_inst<0b0, S, mnemonic>;
|
||||
|
||||
def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR16>;
|
||||
|
||||
def : Pat<(op imm0_3:$tile, (nxv8i1 PPR3bAny:$pn), (nxv8i1 PPR3bAny:$pm),
|
||||
(nxv8bf16 ZPR16:$zn), (nxv8bf16 ZPR16:$zm)),
|
||||
(!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
|
||||
}
|
||||
|
||||
multiclass sme_f16_outer_product<bit S, string mnemonic> {
|
||||
def : sme_outer_product_widening_inst<0b1, S, mnemonic>;
|
||||
multiclass sme_f16_outer_product<bit S, string mnemonic, SDPatternOperator op> {
|
||||
def NAME : sme_outer_product_widening_inst<0b1, S, mnemonic>;
|
||||
|
||||
def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR16>;
|
||||
|
||||
def : Pat<(op imm0_3:$tile, (nxv8i1 PPR3bAny:$pn), (nxv8i1 PPR3bAny:$pm),
|
||||
(nxv8f16 ZPR16:$zn), (nxv8f16 ZPR16:$zm)),
|
||||
(!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -0,0 +1,126 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
define void @bfmopa(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
|
||||
; CHECK-LABEL: bfmopa:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bfmopa za0.s, p0/m, p1/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.mopa.wide.nxv8bf16(i64 0, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fmopa(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm) {
|
||||
; CHECK-LABEL: fmopa:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmopa za1.s, p0/m, p1/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.mopa.wide.nxv8f16(i64 1, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @smopa_s(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
|
||||
; CHECK-LABEL: smopa_s:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: smopa za2.s, p0/m, p1/m, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.smopa.wide.nxv16i8(i64 2, <vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @smopa_d(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
|
||||
; CHECK-LABEL: smopa_d:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: smopa za0.d, p0/m, p1/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.smopa.wide.nxv8i16(i64 0, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @umopa_s(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
|
||||
; CHECK-LABEL: umopa_s:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umopa za3.s, p0/m, p1/m, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.umopa.wide.nxv16i8(i64 3, <vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @umopa_d(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
|
||||
; CHECK-LABEL: umopa_d:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umopa za1.d, p0/m, p1/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.umopa.wide.nxv8i16(i64 1, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fmopa_s(<vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x float> %zn, <vscale x 4 x float> %zm) {
|
||||
; CHECK-LABEL: fmopa_s:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmopa za0.s, p0/m, p1/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.mopa.nxv4f32(i64 0, <vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x float> %zn, <vscale x 4 x float> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fmopa_d(<vscale x 2 x i1> %pn, <vscale x 2 x i1> %pm, <vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #1 {
|
||||
; CHECK-LABEL: fmopa_d:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmopa za2.d, p0/m, p1/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.mopa.nxv2f64(i64 2, <vscale x 2 x i1> %pn, <vscale x 2 x i1> %pm, <vscale x 2 x double> %zn, <vscale x 2 x double> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sumopa_s(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
|
||||
; CHECK-LABEL: sumopa_s:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sumopa za1.s, p0/m, p1/m, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.sumopa.wide.nxv16i8(i64 1, <vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sumopa_d(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
|
||||
; CHECK-LABEL: sumopa_d:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sumopa za3.d, p0/m, p1/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.sumopa.wide.nxv8i16(i64 3, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @usmopa_s(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
|
||||
; CHECK-LABEL: usmopa_s:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: usmopa za2.s, p0/m, p1/m, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.usmopa.wide.nxv16i8(i64 2, <vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @usmopa_d(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
|
||||
; CHECK-LABEL: usmopa_d:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: usmopa za7.d, p0/m, p1/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.usmopa.wide.nxv8i16(i64 7, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { "target-features"="+sme-i64" }
|
||||
attributes #1 = { "target-features"="+sme-f64" }
|
||||
|
||||
declare void @llvm.aarch64.sme.mopa.wide.nxv8bf16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
|
||||
declare void @llvm.aarch64.sme.mopa.wide.nxv8f16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
|
||||
declare void @llvm.aarch64.sme.mopa.nxv4f32(i64, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare void @llvm.aarch64.sme.mopa.nxv2f64(i64, <vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
declare void @llvm.aarch64.sme.smopa.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare void @llvm.aarch64.sme.smopa.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare void @llvm.aarch64.sme.umopa.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare void @llvm.aarch64.sme.umopa.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare void @llvm.aarch64.sme.sumopa.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare void @llvm.aarch64.sme.sumopa.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare void @llvm.aarch64.sme.usmopa.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare void @llvm.aarch64.sme.usmopa.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
define void @bfmops(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
|
||||
; CHECK-LABEL: bfmops:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bfmops za0.s, p0/m, p1/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.mops.wide.nxv8bf16(i64 0, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fmops(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm) {
|
||||
; CHECK-LABEL: fmops:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmops za1.s, p0/m, p1/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.mops.wide.nxv8f16(i64 1, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @smops_s(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
|
||||
; CHECK-LABEL: smops_s:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: smops za2.s, p0/m, p1/m, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.smops.wide.nxv16i8(i64 2, <vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @smops_d(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
|
||||
; CHECK-LABEL: smops_d:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: smops za0.d, p0/m, p1/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.smops.wide.nxv8i16(i64 0, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @umops_s(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
|
||||
; CHECK-LABEL: umops_s:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umops za3.s, p0/m, p1/m, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.umops.wide.nxv16i8(i64 3, <vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @umops_d(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
|
||||
; CHECK-LABEL: umops_d:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umops za1.d, p0/m, p1/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.umops.wide.nxv8i16(i64 1, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fmops_s(<vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x float> %zn, <vscale x 4 x float> %zm) {
|
||||
; CHECK-LABEL: fmops_s:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmops za0.s, p0/m, p1/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.mops.nxv4f32(i64 0, <vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x float> %zn, <vscale x 4 x float> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fmops_d(<vscale x 2 x i1> %pn, <vscale x 2 x i1> %pm, <vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #1 {
|
||||
; CHECK-LABEL: fmops_d:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmops za2.d, p0/m, p1/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.mops.nxv2f64(i64 2, <vscale x 2 x i1> %pn, <vscale x 2 x i1> %pm, <vscale x 2 x double> %zn, <vscale x 2 x double> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sumops_s(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
|
||||
; CHECK-LABEL: sumops_s:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sumops za1.s, p0/m, p1/m, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.sumops.wide.nxv16i8(i64 1, <vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sumops_d(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
|
||||
; CHECK-LABEL: sumops_d:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sumops za3.d, p0/m, p1/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.sumops.wide.nxv8i16(i64 3, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @usmops_s(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
|
||||
; CHECK-LABEL: usmops_s:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: usmops za2.s, p0/m, p1/m, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.usmops.wide.nxv16i8(i64 2, <vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @usmops_d(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
|
||||
; CHECK-LABEL: usmops_d:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: usmops za7.d, p0/m, p1/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sme.usmops.wide.nxv8i16(i64 7, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { "target-features"="+sme-i64" }
|
||||
attributes #1 = { "target-features"="+sme-f64" }
|
||||
|
||||
declare void @llvm.aarch64.sme.mops.wide.nxv8bf16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
|
||||
declare void @llvm.aarch64.sme.mops.wide.nxv8f16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
|
||||
declare void @llvm.aarch64.sme.mops.nxv4f32(i64, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
|
||||
declare void @llvm.aarch64.sme.mops.nxv2f64(i64, <vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
|
||||
declare void @llvm.aarch64.sme.smops.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare void @llvm.aarch64.sme.smops.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare void @llvm.aarch64.sme.umops.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare void @llvm.aarch64.sme.umops.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare void @llvm.aarch64.sme.sumops.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare void @llvm.aarch64.sme.sumops.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare void @llvm.aarch64.sme.usmops.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare void @llvm.aarch64.sme.usmops.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
Loading…
Reference in New Issue