forked from OSchip/llvm-project
Implement Android versions of __clear_cache for arm32 & mips.
The MIPS version was reviewed by myself. The ARM version was reviewed by JF Bastien. Patch by Narayan Kamath <narayan@google.com>. llvm-svn: 203674
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@ -17,6 +17,14 @@
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#include <machine/sysarch.h>
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#endif
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#if defined(ANDROID) && defined(__mips__)
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#include <sys/cachectl.h>
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#endif
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#if defined(ANDROID) && defined(__arm__)
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#include <asm/unistd.h>
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#endif
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/*
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* The compiler generates calls to __clear_cache() when creating
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* trampoline functions on the stack for use with nested functions.
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@ -32,13 +40,31 @@ __clear_cache(void* start, void* end)
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* Intel processors have a unified instruction and data cache
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* so there is nothing to do
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*/
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#elif defined(__NetBSD__) && defined(__arm__)
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struct arm_sync_icache_args arg;
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#elif defined(__arm__) && !defined(__APPLE__)
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#if defined(__NetBSD__)
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struct arm_sync_icache_args arg;
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arg.addr = (uintptr_t)start;
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arg.len = (uintptr_t)end - (uintptr_t)start;
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arg.addr = (uintptr_t)start;
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arg.len = (uintptr_t)end - (uintptr_t)start;
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sysarch(ARM_SYNC_ICACHE, &arg);
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sysarch(ARM_SYNC_ICACHE, &arg);
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#elif defined(ANDROID)
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const register int start_reg __asm("r0") = (int) (intptr_t) start;
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const register int end_reg __asm("r1") = (int) (intptr_t) end;
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const register int flags __asm("r2") = 0;
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const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush;
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__asm __volatile("svc 0x0" : "=r"(start_reg)
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: "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags) : "r0");
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if (start_reg != 0) {
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compilerrt_abort();
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}
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#else
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compilerrt_abort();
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#endif
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#elif defined(ANDROID) && defined(__mips__)
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const uintptr_t start_int = (uintptr_t) start;
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const uintptr_t end_int = (uintptr_t) end;
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_flush_cache(start, (end_int - start_int), BCACHE);
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#elif defined(__aarch64__) && !defined(__APPLE__)
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uint64_t xstart = (uint64_t)(uintptr_t) start;
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uint64_t xend = (uint64_t)(uintptr_t) end;
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