forked from OSchip/llvm-project
[mips] Define instruction itineraries IIArith and IILogic.
No functionality change. llvm-svn: 187468
This commit is contained in:
Akira Hatanaka
parent
2ac682a671
commit
f8fff213d5
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@ -8,13 +8,11 @@ let isCodeGenOnly = 1 in {
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SLTI_FM_MM<0x24>;
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def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
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SLTI_FM_MM<0x2c>;
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def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16,
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and>,
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def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd>,
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ADDI_FM_MM<0x34>;
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def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
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def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd>,
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ADDI_FM_MM<0x14>;
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def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16,
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xor>,
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def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd>,
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ADDI_FM_MM<0x1c>;
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def LUi_MM : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM_MM;
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@ -78,31 +78,35 @@ let isPseudo = 1 in {
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let DecoderNamespace = "Mips64" in {
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/// Arithmetic Instructions (ALU Immediate)
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def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>;
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def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, immSExt16, add>,
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def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, IIArith,
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immSExt16, add>,
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ADDI_FM<0x19>, IsAsCheapAsAMove;
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def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, immZExt16, and>,
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def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
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and>,
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ADDI_FM<0xc>;
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def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
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SLTI_FM<0xa>;
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def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
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SLTI_FM<0xb>;
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def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, immZExt16, or>,
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def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
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or>,
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ADDI_FM<0xd>;
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def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, immZExt16, xor>,
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def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
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xor>,
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ADDI_FM<0xe>;
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def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>;
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def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIAlu, add>,
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def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIArith, add>,
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ADD_FM<0, 0x2d>;
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def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIAlu, sub>,
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def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIArith, sub>,
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ADD_FM<0, 0x2f>;
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def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
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def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
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def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>;
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def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>;
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def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
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def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIArith, and>, ADD_FM<0, 0x24>;
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def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIArith, or>, ADD_FM<0, 0x25>;
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def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIArith, xor>, ADD_FM<0, 0x26>;
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def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>;
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/// Shift Instructions
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@ -232,11 +236,11 @@ let Pattern = []<dag> in {
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let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
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def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
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"dsll\t$rd, $rt, 32", [], IIAlu>;
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"dsll\t$rd, $rt, 32", [], IIArith>;
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def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
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"sll\t$rd, $rt, 0", [], IIAlu>;
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"sll\t$rd, $rt, 0", [], IIArith>;
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def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
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"sll\t$rd, $rt, 0", [], IIAlu>;
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"sll\t$rd, $rt, 0", [], IIArith>;
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}
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}
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//===----------------------------------------------------------------------===//
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@ -171,16 +171,16 @@ let Predicates = [IsFP64bit, HasStdEnc],
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}
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}
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def MOVT_I : CMov_F_I_FT<"movt", CPURegsOpnd, IIAlu, MipsCMovFP_T>,
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def MOVT_I : CMov_F_I_FT<"movt", CPURegsOpnd, IIArith, MipsCMovFP_T>,
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CMov_F_I_FM<1>;
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def MOVT_I64 : CMov_F_I_FT<"movt", CPU64RegsOpnd, IIAlu, MipsCMovFP_T>,
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def MOVT_I64 : CMov_F_I_FT<"movt", CPU64RegsOpnd, IIArith, MipsCMovFP_T>,
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CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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}
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def MOVF_I : CMov_F_I_FT<"movf", CPURegsOpnd, IIAlu, MipsCMovFP_F>,
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def MOVF_I : CMov_F_I_FT<"movf", CPURegsOpnd, IIArith, MipsCMovFP_F>,
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CMov_F_I_FM<0>;
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def MOVF_I64 : CMov_F_I_FT<"movf", CPU64RegsOpnd, IIAlu, MipsCMovFP_F>,
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def MOVF_I64 : CMov_F_I_FT<"movf", CPU64RegsOpnd, IIArith, MipsCMovFP_F>,
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CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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}
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@ -390,12 +390,13 @@ class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
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// Arithmetic and logical instructions with 2 register operands.
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class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
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InstrItinClass Itin = NoItinerary,
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SDPatternOperator imm_type = null_frag,
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SDPatternOperator OpNode = null_frag> :
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InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
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!strconcat(opstr, "\t$rt, $rs, $imm16"),
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[(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
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IIAlu, FrmI, opstr> {
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Itin, FrmI, opstr> {
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let isReMaterializable = 1;
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let TwoOperandAliasConstraint = "$rs = $rt";
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}
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@ -413,7 +414,7 @@ class MArithR<string opstr, bit isComm = 0> :
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class LogicNOR<string opstr, RegisterOperand RC>:
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InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(opstr, "\t$rd, $rs, $rt"),
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[(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR, opstr> {
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[(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIArith, FrmR, opstr> {
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let isCommutable = 1;
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}
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@ -423,18 +424,18 @@ class shift_rotate_imm<string opstr, Operand ImmOpnd,
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SDPatternOperator PF = null_frag> :
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InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
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!strconcat(opstr, "\t$rd, $rt, $shamt"),
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[(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR, opstr>;
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[(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
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class shift_rotate_reg<string opstr, RegisterOperand RC,
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SDPatternOperator OpNode = null_frag>:
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InstSE<(outs RC:$rd), (ins RC:$rt, CPURegsOpnd:$rs),
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!strconcat(opstr, "\t$rd, $rt, $rs"),
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[(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR, opstr>;
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[(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIArith, FrmR, opstr>;
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// Load Upper Imediate
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class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
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InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
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[], IIAlu, FrmI>, IsAsCheapAsAMove {
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[], IIArith, FrmI>, IsAsCheapAsAMove {
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let neverHasSideEffects = 1;
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let isReMaterializable = 1;
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}
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@ -736,12 +737,12 @@ class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> :
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// Count Leading Ones/Zeros in Word
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class CountLeading0<string opstr, RegisterOperand RO>:
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InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
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[(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>,
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[(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>,
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Requires<[HasBitCount, HasStdEnc]>;
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class CountLeading1<string opstr, RegisterOperand RO>:
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InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
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[(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>,
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[(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>,
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Requires<[HasBitCount, HasStdEnc]>;
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@ -763,7 +764,7 @@ class SubwordSwap<string opstr, RegisterOperand RO>:
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// Read Hardware
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class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> :
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InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
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IIAlu, FrmR>;
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IIArith, FrmR>;
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// Ext and Ins
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class ExtBase<string opstr, RegisterOperand RO>:
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@ -891,25 +892,29 @@ let isPseudo = 1 in {
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//===----------------------------------------------------------------------===//
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/// Arithmetic Instructions (ALU Immediate)
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def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>,
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def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, IIArith, immSExt16,
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add>,
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ADDI_FM<0x9>, IsAsCheapAsAMove;
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def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
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def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>,
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SLTI_FM<0xa>;
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def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
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SLTI_FM<0xb>;
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def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>,
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def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, IILogic, immZExt16,
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and>,
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ADDI_FM<0xc>;
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def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
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def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, IILogic, immZExt16,
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or>,
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ADDI_FM<0xd>;
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def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>,
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def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, IILogic, immZExt16,
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xor>,
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ADDI_FM<0xe>;
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def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>,
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def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIArith, add>,
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ADD_FM<0, 0x21>;
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def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>,
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def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIArith, sub>,
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ADD_FM<0, 0x23>;
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def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>,
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ADD_FM<0x1c, 2>;
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@ -917,11 +922,11 @@ def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
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def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
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def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
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def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
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def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>,
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def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IILogic, and>,
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ADD_FM<0, 0x24>;
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def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>,
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def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IILogic, or>,
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ADD_FM<0, 0x25>;
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def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>,
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def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IILogic, xor>,
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ADD_FM<0, 0x26>;
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def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;
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@ -17,6 +17,8 @@ def IMULDIV : FuncUnit;
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// Instruction Itinerary classes used for Mips
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//===----------------------------------------------------------------------===//
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def IIAlu : InstrItinClass;
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def IIArith : InstrItinClass;
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def IILogic : InstrItinClass;
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def IILoad : InstrItinClass;
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def IIStore : InstrItinClass;
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def IIXfer : InstrItinClass;
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@ -48,6 +50,8 @@ def IIPseudo : InstrItinClass;
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//===----------------------------------------------------------------------===//
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def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
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InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIArith , [InstrStage<1, [ALU]>]>,
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InstrItinData<IILogic , [InstrStage<1, [ALU]>]>,
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InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
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InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIXfer , [InstrStage<2, [ALU]>]>,
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