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[mips] Define instruction itineraries IIArith and IILogic. 

No functionality change.

llvm-svn: 187468
This commit is contained in:
Akira Hatanaka 2013-07-31 00:55:34 +00:00
parent 2ac682a671
commit f8fff213d5
5 changed files with 49 additions and 38 deletions
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8
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -8,13 +8,11 @@ let isCodeGenOnly = 1 in {
SLTI_FM_MM<0x24>; SLTI_FM_MM<0x24>;
def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
SLTI_FM_MM<0x2c>; SLTI_FM_MM<0x2c>;
def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd>,
and>,
ADDI_FM_MM<0x34>; ADDI_FM_MM<0x34>;
def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd>,
ADDI_FM_MM<0x14>; ADDI_FM_MM<0x14>;
def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd>,
xor>,
ADDI_FM_MM<0x1c>; ADDI_FM_MM<0x1c>;
def LUi_MM : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM_MM; def LUi_MM : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM_MM;

28
llvm/lib/Target/Mips/Mips64InstrInfo.td
View File

@ -78,31 +78,35 @@ let isPseudo = 1 in {
let DecoderNamespace = "Mips64" in { let DecoderNamespace = "Mips64" in {
/// Arithmetic Instructions (ALU Immediate) /// Arithmetic Instructions (ALU Immediate)
def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>; def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>;
def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, immSExt16, add>, def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, IIArith,
immSExt16, add>,
ADDI_FM<0x19>, IsAsCheapAsAMove; ADDI_FM<0x19>, IsAsCheapAsAMove;
def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, immZExt16, and>, def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
and>,
ADDI_FM<0xc>; ADDI_FM<0xc>;
def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>, def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
SLTI_FM<0xa>; SLTI_FM<0xa>;
def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>, def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
SLTI_FM<0xb>; SLTI_FM<0xb>;
def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, immZExt16, or>, def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
or>,
ADDI_FM<0xd>; ADDI_FM<0xd>;
def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, immZExt16, xor>, def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
xor>,
ADDI_FM<0xe>; ADDI_FM<0xe>;
def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM; def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
/// Arithmetic Instructions (3-Operand, R-Type) /// Arithmetic Instructions (3-Operand, R-Type)
def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>; def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>;
def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIAlu, add>, def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIArith, add>,
ADD_FM<0, 0x2d>; ADD_FM<0, 0x2d>;
def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIAlu, sub>, def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIArith, sub>,
ADD_FM<0, 0x2f>; ADD_FM<0, 0x2f>;
def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>; def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>; def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIArith, and>, ADD_FM<0, 0x24>;
def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIArith, or>, ADD_FM<0, 0x25>;
def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIArith, xor>, ADD_FM<0, 0x26>;
def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>; def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>;
/// Shift Instructions /// Shift Instructions
@ -232,11 +236,11 @@ let Pattern = []<dag> in {
let isCodeGenOnly = 1, rs = 0, shamt = 0 in { let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
"dsll\t$rd, $rt, 32", [], IIAlu>; "dsll\t$rd, $rt, 32", [], IIArith>;
def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
"sll\t$rd, $rt, 0", [], IIAlu>; "sll\t$rd, $rt, 0", [], IIArith>;
def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
"sll\t$rd, $rt, 0", [], IIAlu>; "sll\t$rd, $rt, 0", [], IIArith>;
} }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

8
llvm/lib/Target/Mips/MipsCondMov.td
View File

@ -171,16 +171,16 @@ let Predicates = [IsFP64bit, HasStdEnc],
} }
} }
def MOVT_I : CMov_F_I_FT<"movt", CPURegsOpnd, IIAlu, MipsCMovFP_T>, def MOVT_I : CMov_F_I_FT<"movt", CPURegsOpnd, IIArith, MipsCMovFP_T>,
CMov_F_I_FM<1>; CMov_F_I_FM<1>;
def MOVT_I64 : CMov_F_I_FT<"movt", CPU64RegsOpnd, IIAlu, MipsCMovFP_T>, def MOVT_I64 : CMov_F_I_FT<"movt", CPU64RegsOpnd, IIArith, MipsCMovFP_T>,
CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]> { CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]> {
let DecoderNamespace = "Mips64"; let DecoderNamespace = "Mips64";
} }
def MOVF_I : CMov_F_I_FT<"movf", CPURegsOpnd, IIAlu, MipsCMovFP_F>, def MOVF_I : CMov_F_I_FT<"movf", CPURegsOpnd, IIArith, MipsCMovFP_F>,
CMov_F_I_FM<0>; CMov_F_I_FM<0>;
def MOVF_I64 : CMov_F_I_FT<"movf", CPU64RegsOpnd, IIAlu, MipsCMovFP_F>, def MOVF_I64 : CMov_F_I_FT<"movf", CPU64RegsOpnd, IIArith, MipsCMovFP_F>,
CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]> { CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]> {
let DecoderNamespace = "Mips64"; let DecoderNamespace = "Mips64";
} }

39
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -390,12 +390,13 @@ class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
// Arithmetic and logical instructions with 2 register operands. // Arithmetic and logical instructions with 2 register operands.
class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
InstrItinClass Itin = NoItinerary,
SDPatternOperator imm_type = null_frag, SDPatternOperator imm_type = null_frag,
SDPatternOperator OpNode = null_frag> : SDPatternOperator OpNode = null_frag> :
InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
!strconcat(opstr, "\t$rt, $rs, $imm16"), !strconcat(opstr, "\t$rt, $rs, $imm16"),
[(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
IIAlu, FrmI, opstr> { Itin, FrmI, opstr> {
let isReMaterializable = 1; let isReMaterializable = 1;
let TwoOperandAliasConstraint = "$rs = $rt"; let TwoOperandAliasConstraint = "$rs = $rt";
} }
@ -413,7 +414,7 @@ class MArithR<string opstr, bit isComm = 0> :
class LogicNOR<string opstr, RegisterOperand RC>: class LogicNOR<string opstr, RegisterOperand RC>:
InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
!strconcat(opstr, "\t$rd, $rs, $rt"), !strconcat(opstr, "\t$rd, $rs, $rt"),
[(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR, opstr> { [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIArith, FrmR, opstr> {
let isCommutable = 1; let isCommutable = 1;
} }
@ -423,18 +424,18 @@ class shift_rotate_imm<string opstr, Operand ImmOpnd,
SDPatternOperator PF = null_frag> : SDPatternOperator PF = null_frag> :
InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
!strconcat(opstr, "\t$rd, $rt, $shamt"), !strconcat(opstr, "\t$rd, $rt, $shamt"),
[(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR, opstr>; [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
class shift_rotate_reg<string opstr, RegisterOperand RC, class shift_rotate_reg<string opstr, RegisterOperand RC,
SDPatternOperator OpNode = null_frag>: SDPatternOperator OpNode = null_frag>:
InstSE<(outs RC:$rd), (ins RC:$rt, CPURegsOpnd:$rs), InstSE<(outs RC:$rd), (ins RC:$rt, CPURegsOpnd:$rs),
!strconcat(opstr, "\t$rd, $rt, $rs"), !strconcat(opstr, "\t$rd, $rt, $rs"),
[(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR, opstr>; [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIArith, FrmR, opstr>;
// Load Upper Imediate // Load Upper Imediate
class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
[], IIAlu, FrmI>, IsAsCheapAsAMove { [], IIArith, FrmI>, IsAsCheapAsAMove {
let neverHasSideEffects = 1; let neverHasSideEffects = 1;
let isReMaterializable = 1; let isReMaterializable = 1;
} }
@ -736,12 +737,12 @@ class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> :
// Count Leading Ones/Zeros in Word // Count Leading Ones/Zeros in Word
class CountLeading0<string opstr, RegisterOperand RO>: class CountLeading0<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
[(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>,
Requires<[HasBitCount, HasStdEnc]>; Requires<[HasBitCount, HasStdEnc]>;
class CountLeading1<string opstr, RegisterOperand RO>: class CountLeading1<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
[(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>,
Requires<[HasBitCount, HasStdEnc]>; Requires<[HasBitCount, HasStdEnc]>;
@ -763,7 +764,7 @@ class SubwordSwap<string opstr, RegisterOperand RO>:
// Read Hardware // Read Hardware
class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> :
InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
IIAlu, FrmR>; IIArith, FrmR>;
// Ext and Ins // Ext and Ins
class ExtBase<string opstr, RegisterOperand RO>: class ExtBase<string opstr, RegisterOperand RO>:
@ -891,25 +892,29 @@ let isPseudo = 1 in {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// Arithmetic Instructions (ALU Immediate) /// Arithmetic Instructions (ALU Immediate)
def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, IIArith, immSExt16,
add>,
ADDI_FM<0x9>, IsAsCheapAsAMove; ADDI_FM<0x9>, IsAsCheapAsAMove;
def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>,
SLTI_FM<0xa>; SLTI_FM<0xa>;
def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
SLTI_FM<0xb>; SLTI_FM<0xb>;
def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, IILogic, immZExt16,
and>,
ADDI_FM<0xc>; ADDI_FM<0xc>;
def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, IILogic, immZExt16,
or>,
ADDI_FM<0xd>; ADDI_FM<0xd>;
def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, IILogic, immZExt16,
xor>,
ADDI_FM<0xe>; ADDI_FM<0xe>;
def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
/// Arithmetic Instructions (3-Operand, R-Type) /// Arithmetic Instructions (3-Operand, R-Type)
def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIArith, add>,
ADD_FM<0, 0x21>; ADD_FM<0, 0x21>;
def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIArith, sub>,
ADD_FM<0, 0x23>; ADD_FM<0, 0x23>;
def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>,
ADD_FM<0x1c, 2>; ADD_FM<0x1c, 2>;
@ -917,11 +922,11 @@ def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IILogic, and>,
ADD_FM<0, 0x24>; ADD_FM<0, 0x24>;
def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IILogic, or>,
ADD_FM<0, 0x25>; ADD_FM<0, 0x25>;
def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IILogic, xor>,
ADD_FM<0, 0x26>; ADD_FM<0, 0x26>;
def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;

4
llvm/lib/Target/Mips/MipsSchedule.td
View File

@ -17,6 +17,8 @@ def IMULDIV : FuncUnit;
// Instruction Itinerary classes used for Mips // Instruction Itinerary classes used for Mips
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def IIAlu : InstrItinClass; def IIAlu : InstrItinClass;
def IIArith : InstrItinClass;
def IILogic : InstrItinClass;
def IILoad : InstrItinClass; def IILoad : InstrItinClass;
def IIStore : InstrItinClass; def IIStore : InstrItinClass;
def IIXfer : InstrItinClass; def IIXfer : InstrItinClass;
@ -48,6 +50,8 @@ def IIPseudo : InstrItinClass;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>, InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
InstrItinData<IIArith , [InstrStage<1, [ALU]>]>,
InstrItinData<IILogic , [InstrStage<1, [ALU]>]>,
InstrItinData<IILoad , [InstrStage<3, [ALU]>]>, InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
InstrItinData<IIStore , [InstrStage<1, [ALU]>]>, InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
InstrItinData<IIXfer , [InstrStage<2, [ALU]>]>, InstrItinData<IIXfer , [InstrStage<2, [ALU]>]>,