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[RISCV] Don't create LMUL=8 pseudo instructions for ternary widening arithmetic instructions 

These instructions produce 2*SEW result so the input can't have
an LMUL=8 or the result would need a non-existant LMUL=16. So
only create pseudos for LMUL up to 4.

Differential Revision: https://reviews.llvm.org/D95189
This commit is contained in:
Craig Topper 2021-01-21 17:51:29 -08:00
parent 3dedad475d
commit f8f1b20e6b
1 changed files with 2 additions and 2 deletions
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4
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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@ -1581,13 +1581,13 @@ multiclass VPseudoTernaryV_VX_AAXA<bit IsFloat, string Constraint = ""> {
multiclass VPseudoTernaryW_VV { multiclass VPseudoTernaryW_VV {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
foreach m = MxList.m in foreach m = MxList.m[0-5] in
defm _VV : VPseudoTernary<m.wvrclass, m.vrclass, m.vrclass, m, constraint>; defm _VV : VPseudoTernary<m.wvrclass, m.vrclass, m.vrclass, m, constraint>;
} }
multiclass VPseudoTernaryW_VX<bit IsFloat> { multiclass VPseudoTernaryW_VX<bit IsFloat> {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
foreach m = MxList.m in foreach m = MxList.m[0-5] in
defm !if(IsFloat, "_VF", "_VX") : VPseudoTernary<m.wvrclass, defm !if(IsFloat, "_VF", "_VX") : VPseudoTernary<m.wvrclass,
!if(IsFloat, FPR32, GPR), m.vrclass, m, constraint>; !if(IsFloat, FPR32, GPR), m.vrclass, m, constraint>;
} }