maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Fix two typos I found in comments. 

llvm-svn: 9806
This commit is contained in:
Brian Gaeke 2003-11-08 18:12:24 +00:00
parent 14b5d5a98e
commit f8cb2419ee
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/Sparc/SparcRegInfo.cpp
View File

@ -760,7 +760,7 @@ UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
#else
// Default to using register g2 for holding large offsets
// Default to using register g4 for holding large offsets
OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
SparcIntRegClass::g4);
#endif
@ -845,7 +845,7 @@ UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
#else
// Default to using register g2 for holding large offsets
// Default to using register g4 for holding large offsets
OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
SparcIntRegClass::g4);
#endif

2
llvm/lib/Target/Sparc/SparcV9_Reg.td
View File

@ -32,7 +32,7 @@ let Namespace = "SparcV9" in {
// For fun, specify a register class.
//
// FIXME: the register order should be defined in terms of the prefered
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,