forked from OSchip/llvm-project
Using branch probability to guide critical edge splitting.
Summary: The original heuristic to break critical edge during machine sink is relatively conservertive: when there is only one instruction sinkable to the critical edge, it is likely that the machine sink pass will not break the critical edge. This leads to many speculative instructions executed at runtime. However, with profile info, we could model the splitting benefits: if the critical edge has 50% taken rate, it would always be beneficial to split the critical edge to avoid the speculated runtime instructions. This patch uses profile to guide critical edge splitting in machine sink pass. The performance impact on speccpu2006 on Intel sandybridge machines: spec/2006/fp/C++/444.namd 25.3 +0.26% spec/2006/fp/C++/447.dealII 45.96 -0.10% spec/2006/fp/C++/450.soplex 41.97 +1.49% spec/2006/fp/C++/453.povray 36.83 -0.96% spec/2006/fp/C/433.milc 23.81 +0.32% spec/2006/fp/C/470.lbm 41.17 +0.34% spec/2006/fp/C/482.sphinx3 48.13 +0.69% spec/2006/int/C++/471.omnetpp 22.45 +3.25% spec/2006/int/C++/473.astar 21.35 -2.06% spec/2006/int/C++/483.xalancbmk 36.02 -2.39% spec/2006/int/C/400.perlbench 33.7 -0.17% spec/2006/int/C/401.bzip2 22.9 +0.52% spec/2006/int/C/403.gcc 32.42 -0.54% spec/2006/int/C/429.mcf 39.59 +0.19% spec/2006/int/C/445.gobmk 26.98 -0.00% spec/2006/int/C/456.hmmer 24.52 -0.18% spec/2006/int/C/458.sjeng 28.26 +0.02% spec/2006/int/C/462.libquantum 55.44 +3.74% spec/2006/int/C/464.h264ref 46.67 -0.39% geometric mean +0.20% Manually checked 473 and 471 to verify the diff is in the noise range. Reviewers: rengolin, davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24818 llvm-svn: 284545
This commit is contained in:
Dehao Chen
parent
62d0e64e9e
commit
f8ac3d26d5
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@ -24,6 +24,7 @@
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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@ -60,6 +61,15 @@ UseBlockFreqInfo("machine-sink-bfi",
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cl::desc("Use block frequency info to find successors to sink"),
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cl::init(true), cl::Hidden);
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static cl::opt<unsigned> SplitEdgeProbabilityThreshold(
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"machine-sink-split-probability-threshold",
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cl::desc(
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"Percentage threshold for splitting single-instruction critical edge. "
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"If the branch threshold is higher than this threshold, we allow "
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"speculative execution of up to 1 instruction to avoid branching to "
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"splitted critical edge"),
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cl::init(40), cl::Hidden);
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STATISTIC(NumSunk, "Number of machine instructions sunk");
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STATISTIC(NumSplit, "Number of critical edges split");
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STATISTIC(NumCoalesces, "Number of copies coalesced");
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@ -74,6 +84,7 @@ namespace {
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MachinePostDominatorTree *PDT; // Machine post dominator tree
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MachineLoopInfo *LI;
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const MachineBlockFrequencyInfo *MBFI;
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const MachineBranchProbabilityInfo *MBPI;
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AliasAnalysis *AA;
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// Remember which edges have been considered for breaking.
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@ -105,6 +116,7 @@ namespace {
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<MachinePostDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addRequired<MachineBranchProbabilityInfo>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addPreserved<MachinePostDominatorTree>();
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AU.addPreserved<MachineLoopInfo>();
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@ -163,6 +175,7 @@ char MachineSinking::ID = 0;
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char &llvm::MachineSinkingID = MachineSinking::ID;
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INITIALIZE_PASS_BEGIN(MachineSinking, "machine-sink",
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"Machine code sinking", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
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INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
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@ -283,6 +296,7 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
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PDT = &getAnalysis<MachinePostDominatorTree>();
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LI = &getAnalysis<MachineLoopInfo>();
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MBFI = UseBlockFreqInfo ? &getAnalysis<MachineBlockFrequencyInfo>() : nullptr;
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MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
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AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
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bool EverMadeChange = false;
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@ -383,6 +397,10 @@ bool MachineSinking::isWorthBreakingCriticalEdge(MachineInstr &MI,
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if (!MI.isCopy() && !TII->isAsCheapAsAMove(MI))
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return true;
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if (MBPI->getEdgeProbability(From, To) <=
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BranchProbability(SplitEdgeProbabilityThreshold, 100))
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return true;
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// MI is cheap, we probably don't want to break the critical edge for it.
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// However, if this would allow some definitions of its source operands
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// to be sunk then it's probably worth it.
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@ -38,16 +38,14 @@ entry:
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; CHECK-ARMV6-NEXT: uxtb [[DESIRED:r[0-9]+]], r1
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; CHECK-ARMV6-NEXT: [[TRY:.LBB[0-9_]+]]:
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; CHECK-ARMV6-NEXT: ldrexb [[LD:r[0-9]+]], [r0]
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; CHECK-ARMV6-NEXT: mov [[RES:r[0-9]+]], #0
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; CHECK-ARMV6-NEXT: cmp [[LD]], [[DESIRED]]
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; CHECK-ARMV6-NEXT: bne [[END:.LBB[0-9_]+]]
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; CHECK-ARMV6-NEXT: movne [[RES:r[0-9]+]], #0
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; CHECK-ARMV6-NEXT: bxne lr
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; CHECK-ARMV6-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0]
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; CHECK-ARMV6-NEXT: mov [[RES]], #1
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; CHECK-ARMV6-NEXT: cmp [[SUCCESS]], #0
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; CHECK-ARMV6-NEXT: bne [[TRY]]
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; CHECK-ARMV6-NEXT: [[END]]:
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; CHECK-ARMV6-NEXT: mov r0, [[RES]]
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; CHECK-ARMV6-NEXT: bx lr
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; CHECK-ARMV6-NEXT: moveq [[RES]], #1
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; CHECK-ARMV6-NEXT: bxeq lr
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; CHECK-ARMV6-NEXT: b [[TRY]]
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; CHECK-THUMBV6-LABEL: test_cmpxchg_res_i8:
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; CHECK-THUMBV6: mov [[EXPECTED:r[0-9]+]], r1
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@ -64,20 +62,18 @@ entry:
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; CHECK-ARMV7-LABEL: test_cmpxchg_res_i8:
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; CHECK-ARMV7-NEXT: .fnstart
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; CHECK-ARMV7-NEXT: uxtb [[DESIRED:r[0-9]+]], r1
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; CHECK-ARMV7-NEXT: [[TRY:.LBB[0-9_]+]]:
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; CHECK-ARMV7-NEXT: b [[TRY:.LBB[0-9_]+]]
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; CHECK-ARMV7-NEXT: [[HEAD:.LBB[0-9_]+]]:
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; CHECK-ARMV7-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0]
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; CHECK-ARMV7-NEXT: cmp [[SUCCESS]], #0
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; CHECK-ARMV7-NEXT: moveq [[RES:r[0-9]+]], #1
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; CHECK-ARMV7-NEXT: bxeq lr
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; CHECK-ARMV7-NEXT: [[TRY]]:
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; CHECK-ARMV7-NEXT: ldrexb [[LD:r[0-9]+]], [r0]
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; CHECK-ARMV7-NEXT: cmp [[LD]], [[DESIRED]]
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; CHECK-ARMV7-NEXT: bne [[FAIL:.LBB[0-9_]+]]
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; CHECK-ARMV7-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0]
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; CHECK-ARMV7-NEXT: mov [[RES:r[0-9]+]], #1
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; CHECK-ARMV7-NEXT: cmp [[SUCCESS]], #0
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; CHECK-ARMV7-NEXT: bne [[TRY]]
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; CHECK-ARMV7-NEXT: b [[END:.LBB[0-9_]+]]
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; CHECK-ARMV7-NEXT: [[FAIL]]:
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; CHECK-ARMV7-NEXT: beq [[HEAD]]
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; CHECK-ARMV7-NEXT: clrex
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; CHECK-ARMV7-NEXT: mov [[RES]], #0
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; CHECK-ARMV7-NEXT: [[END]]:
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; CHECK-ARMV7-NEXT: mov r0, [[RES]]
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; CHECK-ARMV7-NEXT: bx lr
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; CHECK-THUMBV7-LABEL: test_cmpxchg_res_i8:
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@ -12,9 +12,9 @@ entry:
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br i1 %0, label %bb2, label %bb
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bb:
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; CHECK: LBB0_2:
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; CHECK: bne LBB0_2
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; CHECK-NOT: b LBB0_2
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; CHECK: LBB0_[[LABEL:[0-9]]]:
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; CHECK: bne LBB0_[[LABEL]]
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; CHECK-NOT: b LBB0_[[LABEL]]
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; CHECK: bx lr
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%list_addr.05 = phi %struct.list_head* [ %2, %bb ], [ %list, %entry ]
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%next.04 = phi %struct.list_head* [ %list_addr.05, %bb ], [ null, %entry ]
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@ -34,14 +34,13 @@ bb2:
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define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: beq LBB1_[[RET:.]]
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%0 = icmp eq i32 %passes, 0 ; <i1> [#uses=1]
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br i1 %0, label %bb5, label %bb.nph15
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; CHECK: LBB1_[[PREHDR:.]]: @ %bb2.preheader
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bb1: ; preds = %bb2.preheader, %bb1
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; CHECK: LBB1_[[BB1:.]]: @ %bb1
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; CHECK: bne LBB1_[[BB1]]
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; CHECK: LBB1_[[BB3:.]]: @ %bb3
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; CHECK: LBB1_[[PREHDR:.]]: @ %bb2.preheader
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; CHECK: blt LBB1_[[BB3]]
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%indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %bb2.preheader ] ; <i32> [#uses=2]
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%sum.08 = phi i32 [ %2, %bb1 ], [ %sum.110, %bb2.preheader ] ; <i32> [#uses=1]
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%tmp17 = sub i32 %i.07, %indvar ; <i32> [#uses=1]
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@ -53,9 +52,9 @@ bb1: ; preds = %bb2.preheader, %bb1
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br i1 %exitcond, label %bb3, label %bb1
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bb3: ; preds = %bb1, %bb2.preheader
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; CHECK: LBB1_[[BB3:.]]: @ %bb3
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; CHECK: bne LBB1_[[PREHDR]]
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; CHECK-NOT: b LBB1_
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; CHECK: LBB1_[[BB1:.]]: @ %bb1
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; CHECK: bne LBB1_[[BB1]]
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; CHECK: b LBB1_[[BB3]]
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%sum.0.lcssa = phi i32 [ %sum.110, %bb2.preheader ], [ %2, %bb1 ] ; <i32> [#uses=2]
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%3 = add i32 %pass.011, 1 ; <i32> [#uses=2]
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%exitcond18 = icmp eq i32 %3, %passes ; <i1> [#uses=1]
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@ -71,8 +70,6 @@ bb2.preheader: ; preds = %bb3, %bb.nph15
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%sum.110 = phi i32 [ 0, %bb.nph15 ], [ %sum.0.lcssa, %bb3 ] ; <i32> [#uses=2]
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br i1 %4, label %bb1, label %bb3
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; CHECK: LBB1_[[RET]]: @ %bb5
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; CHECK: pop
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bb5: ; preds = %bb3, %entry
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%sum.1.lcssa = phi i32 [ 0, %entry ], [ %sum.0.lcssa, %bb3 ] ; <i32> [#uses=1]
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ret i32 %sum.1.lcssa
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@ -478,12 +478,12 @@ define void @fpcmp_unanalyzable_branch(i1 %cond) {
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; CHECK-LABEL: fpcmp_unanalyzable_branch:
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; CHECK: # BB#0: # %entry
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; CHECK: # BB#1: # %entry.if.then_crit_edge
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; CHECK: .LBB10_4: # %if.then
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; CHECK: .LBB10_5: # %if.end
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; CHECK: .LBB10_5: # %if.then
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; CHECK: .LBB10_6: # %if.end
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; CHECK: # BB#3: # %exit
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; CHECK: jne .LBB10_4
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; CHECK-NEXT: jnp .LBB10_5
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; CHECK-NEXT: jmp .LBB10_4
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; CHECK-NEXT: jnp .LBB10_6
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; CHECK: jmp .LBB10_5
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entry:
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; Note that this branch must be strongly biased toward
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@ -279,28 +279,32 @@ define i64 @ctlz_i64(i64 %x) {
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define i8 @ctlz_i8_zero_test(i8 %n) {
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; X32-LABEL: ctlz_i8_zero_test:
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; X32: # BB#0:
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; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X32-NEXT: movb $8, %al
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; X32-NEXT: testb %cl, %cl
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; X32-NEXT: je .LBB8_2
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; X32-NEXT: # BB#1: # %cond.false
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; X32-NEXT: movzbl %cl, %eax
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; X32-NEXT: movb {{[0-9]+}}(%esp), %al
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; X32-NEXT: testb %al, %al
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; X32-NEXT: je .LBB8_1
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; X32-NEXT: # BB#2: # %cond.false
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; X32-NEXT: movzbl %al, %eax
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; X32-NEXT: bsrl %eax, %eax
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; X32-NEXT: xorl $7, %eax
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; X32-NEXT: .LBB8_2: # %cond.end
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; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; X32-NEXT: retl
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; X32-NEXT: .LBB8_1:
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; X32-NEXT: movb $8, %al
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; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; X32-NEXT: retl
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;
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; X64-LABEL: ctlz_i8_zero_test:
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; X64: # BB#0:
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; X64-NEXT: movb $8, %al
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; X64-NEXT: testb %dil, %dil
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; X64-NEXT: je .LBB8_2
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; X64-NEXT: # BB#1: # %cond.false
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; X64-NEXT: je .LBB8_1
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; X64-NEXT: # BB#2: # %cond.false
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; X64-NEXT: movzbl %dil, %eax
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; X64-NEXT: bsrl %eax, %eax
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; X64-NEXT: xorl $7, %eax
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; X64-NEXT: .LBB8_2: # %cond.end
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; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; X64-NEXT: retq
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; X64-NEXT: .LBB8_1:
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; X64-NEXT: movb $8, %al
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; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; X64-NEXT: retq
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;
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@ -327,26 +331,30 @@ define i8 @ctlz_i8_zero_test(i8 %n) {
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define i16 @ctlz_i16_zero_test(i16 %n) {
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; X32-LABEL: ctlz_i16_zero_test:
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; X32: # BB#0:
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; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movw $16, %ax
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; X32-NEXT: testw %cx, %cx
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; X32-NEXT: je .LBB9_2
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; X32-NEXT: # BB#1: # %cond.false
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; X32-NEXT: bsrw %cx, %ax
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; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: testw %ax, %ax
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; X32-NEXT: je .LBB9_1
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; X32-NEXT: # BB#2: # %cond.false
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; X32-NEXT: bsrw %ax, %ax
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; X32-NEXT: xorl $15, %eax
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; X32-NEXT: .LBB9_2: # %cond.end
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; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; X32-NEXT: retl
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; X32-NEXT: .LBB9_1:
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; X32-NEXT: movw $16, %ax
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; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; X32-NEXT: retl
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;
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; X64-LABEL: ctlz_i16_zero_test:
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; X64: # BB#0:
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; X64-NEXT: movw $16, %ax
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; X64-NEXT: testw %di, %di
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; X64-NEXT: je .LBB9_2
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; X64-NEXT: # BB#1: # %cond.false
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; X64-NEXT: je .LBB9_1
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; X64-NEXT: # BB#2: # %cond.false
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; X64-NEXT: bsrw %di, %ax
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; X64-NEXT: xorl $15, %eax
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; X64-NEXT: .LBB9_2: # %cond.end
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; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; X64-NEXT: retq
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; X64-NEXT: .LBB9_1:
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; X64-NEXT: movw $16, %ax
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; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; X64-NEXT: retq
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;
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@ -367,25 +375,27 @@ define i16 @ctlz_i16_zero_test(i16 %n) {
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define i32 @ctlz_i32_zero_test(i32 %n) {
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; X32-LABEL: ctlz_i32_zero_test:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl $32, %eax
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; X32-NEXT: testl %ecx, %ecx
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; X32-NEXT: je .LBB10_2
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; X32-NEXT: # BB#1: # %cond.false
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; X32-NEXT: bsrl %ecx, %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: testl %eax, %eax
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; X32-NEXT: je .LBB10_1
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; X32-NEXT: # BB#2: # %cond.false
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; X32-NEXT: bsrl %eax, %eax
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; X32-NEXT: xorl $31, %eax
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; X32-NEXT: .LBB10_2: # %cond.end
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; X32-NEXT: retl
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; X32-NEXT: .LBB10_1:
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; X32-NEXT: movl $32, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: ctlz_i32_zero_test:
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; X64: # BB#0:
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; X64-NEXT: movl $32, %eax
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; X64-NEXT: testl %edi, %edi
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; X64-NEXT: je .LBB10_2
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; X64-NEXT: # BB#1: # %cond.false
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; X64-NEXT: je .LBB10_1
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; X64-NEXT: # BB#2: # %cond.false
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; X64-NEXT: bsrl %edi, %eax
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; X64-NEXT: xorl $31, %eax
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; X64-NEXT: .LBB10_2: # %cond.end
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; X64-NEXT: retq
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; X64-NEXT: .LBB10_1:
|
||||
; X64-NEXT: movl $32, %eax
|
||||
; X64-NEXT: retq
|
||||
;
|
||||
; X32-CLZ-LABEL: ctlz_i32_zero_test:
|
||||
|
|
@ -464,26 +474,30 @@ define i64 @ctlz_i64_zero_test(i64 %n) {
|
|||
define i8 @cttz_i8_zero_test(i8 %n) {
|
||||
; X32-LABEL: cttz_i8_zero_test:
|
||||
; X32: # BB#0:
|
||||
; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
|
||||
; X32-NEXT: movb $8, %al
|
||||
; X32-NEXT: testb %cl, %cl
|
||||
; X32-NEXT: je .LBB12_2
|
||||
; X32-NEXT: # BB#1: # %cond.false
|
||||
; X32-NEXT: movzbl %cl, %eax
|
||||
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
|
||||
; X32-NEXT: testb %al, %al
|
||||
; X32-NEXT: je .LBB12_1
|
||||
; X32-NEXT: # BB#2: # %cond.false
|
||||
; X32-NEXT: movzbl %al, %eax
|
||||
; X32-NEXT: bsfl %eax, %eax
|
||||
; X32-NEXT: .LBB12_2: # %cond.end
|
||||
; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
|
||||
; X32-NEXT: retl
|
||||
; X32-NEXT: .LBB12_1
|
||||
; X32-NEXT: movb $8, %al
|
||||
; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: cttz_i8_zero_test:
|
||||
; X64: # BB#0:
|
||||
; X64-NEXT: movb $8, %al
|
||||
; X64-NEXT: testb %dil, %dil
|
||||
; X64-NEXT: je .LBB12_2
|
||||
; X64-NEXT: # BB#1: # %cond.false
|
||||
; X64-NEXT: je .LBB12_1
|
||||
; X64-NEXT: # BB#2: # %cond.false
|
||||
; X64-NEXT: movzbl %dil, %eax
|
||||
; X64-NEXT: bsfl %eax, %eax
|
||||
; X64-NEXT: .LBB12_2: # %cond.end
|
||||
; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
|
||||
; X64-NEXT: retq
|
||||
; X64-NEXT: .LBB12_1:
|
||||
; X64-NEXT: movb $8, %al
|
||||
; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
|
||||
; X64-NEXT: retq
|
||||
;
|
||||
|
|
@ -510,23 +524,25 @@ define i8 @cttz_i8_zero_test(i8 %n) {
|
|||
define i16 @cttz_i16_zero_test(i16 %n) {
|
||||
; X32-LABEL: cttz_i16_zero_test:
|
||||
; X32: # BB#0:
|
||||
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
||||
; X32-NEXT: testw %ax, %ax
|
||||
; X32-NEXT: je .LBB13_1
|
||||
; X32-NEXT: # BB#2: # %cond.false
|
||||
; X32-NEXT: bsfw %ax, %ax
|
||||
; X32-NEXT: retl
|
||||
; X32-NEXT: .LBB13_1
|
||||
; X32-NEXT: movw $16, %ax
|
||||
; X32-NEXT: testw %cx, %cx
|
||||
; X32-NEXT: je .LBB13_2
|
||||
; X32-NEXT: # BB#1: # %cond.false
|
||||
; X32-NEXT: bsfw %cx, %ax
|
||||
; X32-NEXT: .LBB13_2: # %cond.end
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: cttz_i16_zero_test:
|
||||
; X64: # BB#0:
|
||||
; X64-NEXT: movw $16, %ax
|
||||
; X64-NEXT: testw %di, %di
|
||||
; X64-NEXT: je .LBB13_2
|
||||
; X64-NEXT: # BB#1: # %cond.false
|
||||
; X64-NEXT: je .LBB13_1
|
||||
; X64-NEXT: # BB#2: # %cond.false
|
||||
; X64-NEXT: bsfw %di, %ax
|
||||
; X64-NEXT: .LBB13_2: # %cond.end
|
||||
; X64-NEXT: retq
|
||||
; X64-NEXT: .LBB13_1:
|
||||
; X64-NEXT: movw $16, %ax
|
||||
; X64-NEXT: retq
|
||||
;
|
||||
; X32-CLZ-LABEL: cttz_i16_zero_test:
|
||||
|
|
@ -546,23 +562,25 @@ define i16 @cttz_i16_zero_test(i16 %n) {
|
|||
define i32 @cttz_i32_zero_test(i32 %n) {
|
||||
; X32-LABEL: cttz_i32_zero_test:
|
||||
; X32: # BB#0:
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X32-NEXT: testl %eax, %eax
|
||||
; X32-NEXT: je .LBB14_1
|
||||
; X32-NEXT: # BB#2: # %cond.false
|
||||
; X32-NEXT: bsfl %eax, %eax
|
||||
; X32-NEXT: retl
|
||||
; X32-NEXT: .LBB14_1
|
||||
; X32-NEXT: movl $32, %eax
|
||||
; X32-NEXT: testl %ecx, %ecx
|
||||
; X32-NEXT: je .LBB14_2
|
||||
; X32-NEXT: # BB#1: # %cond.false
|
||||
; X32-NEXT: bsfl %ecx, %eax
|
||||
; X32-NEXT: .LBB14_2: # %cond.end
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: cttz_i32_zero_test:
|
||||
; X64: # BB#0:
|
||||
; X64-NEXT: movl $32, %eax
|
||||
; X64-NEXT: testl %edi, %edi
|
||||
; X64-NEXT: je .LBB14_2
|
||||
; X64-NEXT: # BB#1: # %cond.false
|
||||
; X64-NEXT: je .LBB14_1
|
||||
; X64-NEXT: # BB#2: # %cond.false
|
||||
; X64-NEXT: bsfl %edi, %eax
|
||||
; X64-NEXT: .LBB14_2: # %cond.end
|
||||
; X64-NEXT: retq
|
||||
; X64-NEXT: .LBB14_1:
|
||||
; X64-NEXT: movl $32, %eax
|
||||
; X64-NEXT: retq
|
||||
;
|
||||
; X32-CLZ-LABEL: cttz_i32_zero_test:
|
||||
|
|
@ -642,25 +660,27 @@ define i64 @cttz_i64_zero_test(i64 %n) {
|
|||
define i32 @ctlz_i32_fold_cmov(i32 %n) {
|
||||
; X32-LABEL: ctlz_i32_fold_cmov:
|
||||
; X32: # BB#0:
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: orl $1, %ecx
|
||||
; X32-NEXT: movl $32, %eax
|
||||
; X32-NEXT: je .LBB16_2
|
||||
; X32-NEXT: # BB#1: # %cond.false
|
||||
; X32-NEXT: bsrl %ecx, %eax
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X32-NEXT: orl $1, %eax
|
||||
; X32-NEXT: je .LBB16_1
|
||||
; X32-NEXT: # BB#2: # %cond.false
|
||||
; X32-NEXT: bsrl %eax, %eax
|
||||
; X32-NEXT: xorl $31, %eax
|
||||
; X32-NEXT: .LBB16_2: # %cond.end
|
||||
; X32-NEXT: retl
|
||||
; X32-NEXT: .LBB16_1
|
||||
; X32-NEXT: movl $32, %eax
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: ctlz_i32_fold_cmov:
|
||||
; X64: # BB#0:
|
||||
; X64-NEXT: orl $1, %edi
|
||||
; X64-NEXT: movl $32, %eax
|
||||
; X64-NEXT: je .LBB16_2
|
||||
; X64-NEXT: # BB#1: # %cond.false
|
||||
; X64-NEXT: je .LBB16_1
|
||||
; X64-NEXT: # BB#2: # %cond.false
|
||||
; X64-NEXT: bsrl %edi, %eax
|
||||
; X64-NEXT: xorl $31, %eax
|
||||
; X64-NEXT: .LBB16_2: # %cond.end
|
||||
; X64-NEXT: retq
|
||||
; X64-NEXT: .LBB16_1:
|
||||
; X64-NEXT: movl $32, %eax
|
||||
; X64-NEXT: retq
|
||||
;
|
||||
; X32-CLZ-LABEL: ctlz_i32_fold_cmov:
|
||||
|
|
@ -716,26 +736,30 @@ define i32 @ctlz_bsr(i32 %n) {
|
|||
define i32 @ctlz_bsr_zero_test(i32 %n) {
|
||||
; X32-LABEL: ctlz_bsr_zero_test:
|
||||
; X32: # BB#0:
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: movl $32, %eax
|
||||
; X32-NEXT: testl %ecx, %ecx
|
||||
; X32-NEXT: je .LBB18_2
|
||||
; X32-NEXT: # BB#1: # %cond.false
|
||||
; X32-NEXT: bsrl %ecx, %eax
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X32-NEXT: testl %eax, %eax
|
||||
; X32-NEXT: je .LBB18_1
|
||||
; X32-NEXT: # BB#2: # %cond.false
|
||||
; X32-NEXT: bsrl %eax, %eax
|
||||
; X32-NEXT: xorl $31, %eax
|
||||
; X32-NEXT: .LBB18_2: # %cond.end
|
||||
; X32-NEXT: xorl $31, %eax
|
||||
; X32-NEXT: retl
|
||||
; X32-NEXT: .LBB18_1:
|
||||
; X32-NEXT: movl $32, %eax
|
||||
; X32-NEXT: xorl $31, %eax
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: ctlz_bsr_zero_test:
|
||||
; X64: # BB#0:
|
||||
; X64-NEXT: movl $32, %eax
|
||||
; X64-NEXT: testl %edi, %edi
|
||||
; X64-NEXT: je .LBB18_2
|
||||
; X64-NEXT: # BB#1: # %cond.false
|
||||
; X64-NEXT: je .LBB18_1
|
||||
; X64-NEXT: # BB#2: # %cond.false
|
||||
; X64-NEXT: bsrl %edi, %eax
|
||||
; X64-NEXT: xorl $31, %eax
|
||||
; X64-NEXT: .LBB18_2: # %cond.end
|
||||
; X64-NEXT: xorl $31, %eax
|
||||
; X64-NEXT: retq
|
||||
; X64-NEXT: .LBB18_1:
|
||||
; X64-NEXT: movl $32, %eax
|
||||
; X64-NEXT: xorl $31, %eax
|
||||
; X64-NEXT: retq
|
||||
;
|
||||
|
|
|
|||
|
|
@ -10,19 +10,17 @@ define zeroext i1 @search(i32 %needle, i32* nocapture readonly %haystack, i32 %c
|
|||
; CHECK-NEXT: testl %edx, %edx
|
||||
; CHECK-NEXT: jle LBB0_1
|
||||
; CHECK-NEXT: ## BB#4: ## %for.body.preheader
|
||||
; CHECK-NEXT: movslq %edx, %rcx
|
||||
; CHECK-NEXT: xorl %edx, %edx
|
||||
; CHECK-NEXT: movslq %edx, %rax
|
||||
; CHECK-NEXT: xorl %ecx, %ecx
|
||||
; CHECK-NEXT: .p2align 4, 0x90
|
||||
; CHECK-NEXT: LBB0_5: ## %for.body
|
||||
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
|
||||
; ### FIXME: This loop invariant should be hoisted
|
||||
; CHECK-NEXT: movb $1, %al
|
||||
; CHECK-NEXT: cmpl %edi, (%rsi,%rdx,4)
|
||||
; CHECK-NEXT: cmpl %edi, (%rsi,%rcx,4)
|
||||
; CHECK-NEXT: je LBB0_6
|
||||
; CHECK-NEXT: ## BB#2: ## %for.cond
|
||||
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
|
||||
; CHECK-NEXT: incq %rdx
|
||||
; CHECK-NEXT: cmpq %rcx, %rdx
|
||||
; CHECK-NEXT: incq %rcx
|
||||
; CHECK-NEXT: cmpq %rax, %rcx
|
||||
; CHECK-NEXT: jl LBB0_5
|
||||
; ### FIXME: BB#3 and LBB0_1 should be merged
|
||||
; CHECK-NEXT: ## BB#3:
|
||||
|
|
@ -33,7 +31,8 @@ define zeroext i1 @search(i32 %needle, i32* nocapture readonly %haystack, i32 %c
|
|||
; CHECK-NEXT: xorl %eax, %eax
|
||||
; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
|
||||
; CHECK-NEXT: retq
|
||||
; CHECK-NEXT: LBB0_6: ## %cleanup
|
||||
; CHECK-NEXT: LBB0_6:
|
||||
; CHECK-NEXT: movb $1, %al
|
||||
; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
|
||||
; CHECK-NEXT: retq
|
||||
;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s
|
||||
|
||||
; Checks if movl $1 is sinked to critical edge.
|
||||
; CHECK-NOT: movl $1
|
||||
; CHECK: jbe
|
||||
; CHECK: movl $1
|
||||
define i32 @test(i32 %n, i32 %k) nounwind {
|
||||
entry:
|
||||
%cmp = icmp ugt i32 %k, %n
|
||||
br i1 %cmp, label %ifthen, label %ifend, !prof !1
|
||||
|
||||
ifthen:
|
||||
%y = add i32 %k, 2
|
||||
br label %ifend
|
||||
|
||||
ifend:
|
||||
%ret = phi i32 [ 1, %entry ] , [ %y, %ifthen]
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
!1 = !{!"branch_weights", i32 100, i32 1}
|
||||
|
|
@ -14,7 +14,9 @@ forcond.preheader: ; preds = %entry
|
|||
ifthen: ; preds = %entry
|
||||
ret i32 0
|
||||
; CHECK: forbody{{$}}
|
||||
; There should be no mov instruction in the for body.
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: jbe
|
||||
forbody: ; preds = %forbody, %forcond.preheader
|
||||
%indvar = phi i32 [ 0, %forcond.preheader ], [ %divisor.02, %forbody ] ; <i32> [#uses=3]
|
||||
%accumulator.01 = phi i32 [ 1, %forcond.preheader ], [ %div, %forbody ] ; <i32> [#uses=1]
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ forcond.preheader: ; preds = %entry
|
|||
br i1 %cmp44, label %afterfor, label %forbody
|
||||
|
||||
; CHECK: %forcond.preheader
|
||||
; CHECK: movl $1
|
||||
; CHECK: testl
|
||||
; CHECK-NOT: xorl
|
||||
; CHECK-NOT: movl
|
||||
; CHECK-NOT: LBB
|
||||
|
|
@ -24,6 +24,7 @@ forcond.preheader: ; preds = %entry
|
|||
; CHECK: %forbody{{$}}
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: jbe
|
||||
; CHECK: movl $1
|
||||
|
||||
ifthen: ; preds = %entry
|
||||
ret i32 0
|
||||
|
|
|
|||
|
|
@ -37,11 +37,11 @@
|
|||
; ASM-LABEL: loop_csr: # @loop_csr
|
||||
; ASM: #DEBUG_VALUE: loop_csr:o [bit_piece offset=0 size=32] <- 0
|
||||
; ASM: #DEBUG_VALUE: loop_csr:o [bit_piece offset=32 size=32] <- 0
|
||||
; ASM: # BB#1: # %for.body.preheader
|
||||
; ASM: # BB#2: # %for.body.preheader
|
||||
; ASM: xorl %edi, %edi
|
||||
; ASM: xorl %esi, %esi
|
||||
; ASM: .p2align 4, 0x90
|
||||
; ASM: .LBB0_2: # %for.body
|
||||
; ASM: .LBB0_3: # %for.body
|
||||
; ASM: [[ox_start:\.Ltmp[0-9]+]]:
|
||||
; ASM: #DEBUG_VALUE: loop_csr:o [bit_piece offset=0 size=32] <- %EDI
|
||||
; ASM: .cv_loc 0 1 13 11 # t.c:13:11
|
||||
|
|
@ -57,7 +57,7 @@
|
|||
; ASM: movl %eax, %esi
|
||||
; ASM: #DEBUG_VALUE: loop_csr:o [bit_piece offset=32 size=32] <- %ESI
|
||||
; ASM: cmpl n(%rip), %eax
|
||||
; ASM: jl .LBB0_2
|
||||
; ASM: jl .LBB0_3
|
||||
; ASM: [[oy_end:\.Ltmp[0-9]+]]:
|
||||
; ASM: addl %edi, %esi
|
||||
; ASM: movl %esi, %eax
|
||||
|
|
|
|||
Loading…
Reference in New Issue