maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Temporarily backing out this change until we know why some dejagnu tests are failing. 

llvm-svn: 40973
This commit is contained in:
Evan Cheng 2007-08-09 22:25:35 +00:00
parent e32e923a6a
commit f855b626e8
1 changed files with 2 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
llvm/lib/Target/X86/X86RegisterInfo.td
View File

@ -419,12 +419,11 @@ def GR64 : RegisterClass<"X86", [i64], 64,
// GR16, GR32 subclasses which contain registers that have GR8 sub-registers.
// These should only be used for 32-bit mode.
def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL, AH, CH, DH, BH]>;
def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
let SubRegClassList = [GR8_];
let SubRegClassList = [GR8];
}
def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
let SubRegClassList = [GR8_, GR16_];
let SubRegClassList = [GR8, GR16];
}
// Scalar SSE2 floating point registers.