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[ARM] Delay creation of MVE Imm shifts to legalization 

The reasoning for creating VSHLIMM/VSHRsIMM/VSHRuIMM nodes in a combine
- because matching i64 constants is difficult -  does not apply for MVE,
as there are not v2i64 shifts. Delaying the creation of the nodes can
allow extra transforms on target independant shl/shr.
This commit is contained in:
David Green 2022-05-04 22:12:09 +01:00
parent f8d2d8b587
commit f848798b7d
2 changed files with 8 additions and 10 deletions
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2
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -17394,7 +17394,7 @@ static SDValue PerformShiftCombine(SDNode *N,
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (!VT.isVector() || !TLI.isTypeLegal(VT))
return SDValue();
if (ST->hasMVEIntegerOps() && VT == MVT::v2i64)
if (ST->hasMVEIntegerOps())
return SDValue();
int64_t Cnt;

16
llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
View File

@ -230,15 +230,13 @@ entry:
define arm_aapcs_vfpcc <8 x i16> @ext_add_ashr_trunc_i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: ext_add_ashr_trunc_i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u16 q2, q1
; CHECK-NEXT: vmovlb.s16 q3, q0
; CHECK-NEXT: vmovlt.u16 q1, q1
; CHECK-NEXT: vmovlt.s16 q0, q0
; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vadd.i32 q2, q3, q2
; CHECK-NEXT: vshr.u32 q1, q0, #1
; CHECK-NEXT: vshr.u32 q0, q2, #1
; CHECK-NEXT: vmovnt.i32 q0, q1
; CHECK-NEXT: vmovlt.u16 q2, q1
; CHECK-NEXT: vmovlt.s16 q3, q0
; CHECK-NEXT: vmovlb.u16 q1, q1
; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vhadd.s32 q2, q3, q2
; CHECK-NEXT: vhadd.s32 q0, q0, q1
; CHECK-NEXT: vmovnt.i32 q0, q2
; CHECK-NEXT: bx lr
entry:
%sa = sext <8 x i16> %a to <8 x i32>