forked from OSchip/llvm-project
[X86] Improve the rotate ISel test
Summary: - Added 64-bit target testing. - Added 64-bit operand test cases. - Added cases that demonstrate pr30644 Reviewers: RKSimon, craig.topper, igorb Differential Revision: https://reviews.llvm.org/D25401 llvm-svn: 283695
This commit is contained in:
Zvi Rackover
parent
5b10aa1f1e
commit
f841080caf
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@ -1,100 +1,567 @@
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; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
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; RUN: grep "ro[rl]" | count 12
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-linux | FileCheck %s --check-prefix=32
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; RUN: llc < %s -mtriple=x86_64-unknown-linux | FileCheck %s --check-prefix=64
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define i64 @rotl64(i64 %A, i8 %Amt) {
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; 32-LABEL: rotl64:
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; 32: # BB#0:
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; 32-NEXT: pushl %ebx
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; 32-NEXT: .Ltmp0:
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; 32-NEXT: .cfi_def_cfa_offset 8
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; 32-NEXT: pushl %edi
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; 32-NEXT: .Ltmp1:
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; 32-NEXT: .cfi_def_cfa_offset 12
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; 32-NEXT: pushl %esi
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; 32-NEXT: .Ltmp2:
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; 32-NEXT: .cfi_def_cfa_offset 16
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; 32-NEXT: .Ltmp3:
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; 32-NEXT: .cfi_offset %esi, -16
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; 32-NEXT: .Ltmp4:
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; 32-NEXT: .cfi_offset %edi, -12
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; 32-NEXT: .Ltmp5:
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; 32-NEXT: .cfi_offset %ebx, -8
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; 32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; 32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; 32-NEXT: movl {{[0-9]+}}(%esp), %edi
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; 32-NEXT: movl %esi, %eax
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; 32-NEXT: shll %cl, %eax
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; 32-NEXT: movl %edi, %edx
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; 32-NEXT: shldl %cl, %esi, %edx
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; 32-NEXT: testb $32, %cl
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; 32-NEXT: je .LBB0_2
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; 32-NEXT: # BB#1:
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; 32-NEXT: movl %eax, %edx
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; 32-NEXT: xorl %eax, %eax
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; 32-NEXT: .LBB0_2:
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; 32-NEXT: movb $64, %ch
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; 32-NEXT: subb %cl, %ch
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; 32-NEXT: movl %edi, %ebx
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; 32-NEXT: movb %ch, %cl
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; 32-NEXT: shrl %cl, %ebx
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; 32-NEXT: shrdl %cl, %edi, %esi
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; 32-NEXT: testb $32, %ch
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; 32-NEXT: je .LBB0_4
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; 32-NEXT: # BB#3:
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; 32-NEXT: movl %ebx, %esi
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; 32-NEXT: xorl %ebx, %ebx
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; 32-NEXT: .LBB0_4:
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; 32-NEXT: orl %esi, %eax
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; 32-NEXT: orl %ebx, %edx
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; 32-NEXT: popl %esi
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; 32-NEXT: popl %edi
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; 32-NEXT: popl %ebx
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; 32-NEXT: retl
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;
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; 64-LABEL: rotl64:
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; 64: # BB#0:
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; 64-NEXT: movl %esi, %ecx
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; 64-NEXT: rolq %cl, %rdi
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; 64-NEXT: movq %rdi, %rax
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; 64-NEXT: retq
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%shift.upgrd.1 = zext i8 %Amt to i64
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%B = shl i64 %A, %shift.upgrd.1
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%Amt2 = sub i8 64, %Amt
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%shift.upgrd.2 = zext i8 %Amt2 to i64
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%C = lshr i64 %A, %shift.upgrd.2
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%D = or i64 %B, %C
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ret i64 %D
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}
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define i64 @rotr64(i64 %A, i8 %Amt) {
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; 32-LABEL: rotr64:
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; 32: # BB#0:
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; 32-NEXT: pushl %ebx
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; 32-NEXT: .Ltmp6:
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; 32-NEXT: .cfi_def_cfa_offset 8
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; 32-NEXT: pushl %edi
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; 32-NEXT: .Ltmp7:
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; 32-NEXT: .cfi_def_cfa_offset 12
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; 32-NEXT: pushl %esi
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; 32-NEXT: .Ltmp8:
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; 32-NEXT: .cfi_def_cfa_offset 16
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; 32-NEXT: .Ltmp9:
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; 32-NEXT: .cfi_offset %esi, -16
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; 32-NEXT: .Ltmp10:
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; 32-NEXT: .cfi_offset %edi, -12
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; 32-NEXT: .Ltmp11:
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; 32-NEXT: .cfi_offset %ebx, -8
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; 32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; 32-NEXT: movl {{[0-9]+}}(%esp), %edi
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; 32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; 32-NEXT: movl %esi, %edx
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; 32-NEXT: shrl %cl, %edx
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; 32-NEXT: movl %edi, %eax
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; 32-NEXT: shrdl %cl, %esi, %eax
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; 32-NEXT: testb $32, %cl
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; 32-NEXT: je .LBB1_2
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; 32-NEXT: # BB#1:
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; 32-NEXT: movl %edx, %eax
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; 32-NEXT: xorl %edx, %edx
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; 32-NEXT: .LBB1_2:
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; 32-NEXT: movb $64, %ch
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; 32-NEXT: subb %cl, %ch
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; 32-NEXT: movl %edi, %ebx
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; 32-NEXT: movb %ch, %cl
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; 32-NEXT: shll %cl, %ebx
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; 32-NEXT: shldl %cl, %edi, %esi
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; 32-NEXT: testb $32, %ch
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; 32-NEXT: je .LBB1_4
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; 32-NEXT: # BB#3:
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; 32-NEXT: movl %ebx, %esi
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; 32-NEXT: xorl %ebx, %ebx
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; 32-NEXT: .LBB1_4:
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; 32-NEXT: orl %ebx, %eax
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; 32-NEXT: orl %esi, %edx
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; 32-NEXT: popl %esi
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; 32-NEXT: popl %edi
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; 32-NEXT: popl %ebx
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; 32-NEXT: retl
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;
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; 64-LABEL: rotr64:
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; 64: # BB#0:
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; 64-NEXT: movl %esi, %ecx
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; 64-NEXT: rorq %cl, %rdi
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; 64-NEXT: movq %rdi, %rax
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; 64-NEXT: retq
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%shift.upgrd.3 = zext i8 %Amt to i64
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%B = lshr i64 %A, %shift.upgrd.3
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%Amt2 = sub i8 64, %Amt
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%shift.upgrd.4 = zext i8 %Amt2 to i64
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%C = shl i64 %A, %shift.upgrd.4
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%D = or i64 %B, %C
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ret i64 %D
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}
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define i64 @rotli64(i64 %A) {
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; 32-LABEL: rotli64:
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; 32: # BB#0:
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; 32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; 32-NEXT: movl %ecx, %edx
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; 32-NEXT: shldl $5, %eax, %edx
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; 32-NEXT: shldl $5, %ecx, %eax
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; 32-NEXT: retl
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;
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; 64-LABEL: rotli64:
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; 64: # BB#0:
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; 64-NEXT: rolq $5, %rdi
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; 64-NEXT: movq %rdi, %rax
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; 64-NEXT: retq
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%B = shl i64 %A, 5
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%C = lshr i64 %A, 59
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%D = or i64 %B, %C
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ret i64 %D
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}
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define i64 @rotri64(i64 %A) {
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; 32-LABEL: rotri64:
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; 32: # BB#0:
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; 32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; 32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; 32-NEXT: movl %ecx, %eax
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; 32-NEXT: shldl $27, %edx, %eax
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; 32-NEXT: shldl $27, %ecx, %edx
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; 32-NEXT: retl
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;
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; 64-LABEL: rotri64:
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; 64: # BB#0:
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; 64-NEXT: rolq $59, %rdi
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; 64-NEXT: movq %rdi, %rax
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; 64-NEXT: retq
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%B = lshr i64 %A, 5
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%C = shl i64 %A, 59
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%D = or i64 %B, %C
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ret i64 %D
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}
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define i64 @rotl1_64(i64 %A) {
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; 32-LABEL: rotl1_64:
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; 32: # BB#0:
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; 32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; 32-NEXT: movl %ecx, %edx
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; 32-NEXT: shldl $1, %eax, %edx
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; 32-NEXT: shldl $1, %ecx, %eax
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; 32-NEXT: retl
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;
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; 64-LABEL: rotl1_64:
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; 64: # BB#0:
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; 64-NEXT: rolq %rdi
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; 64-NEXT: movq %rdi, %rax
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; 64-NEXT: retq
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%B = shl i64 %A, 1
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%C = lshr i64 %A, 63
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%D = or i64 %B, %C
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ret i64 %D
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}
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define i64 @rotr1_64(i64 %A) {
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; 32-LABEL: rotr1_64:
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; 32: # BB#0:
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; 32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; 32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; 32-NEXT: movl %ecx, %eax
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; 32-NEXT: shldl $31, %edx, %eax
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; 32-NEXT: shldl $31, %ecx, %edx
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; 32-NEXT: retl
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;
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; 64-LABEL: rotr1_64:
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; 64: # BB#0:
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; 64-NEXT: rolq $63, %rdi
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; 64-NEXT: movq %rdi, %rax
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; 64-NEXT: retq
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%B = shl i64 %A, 63
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%C = lshr i64 %A, 1
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%D = or i64 %B, %C
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ret i64 %D
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}
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define i32 @rotl32(i32 %A, i8 %Amt) {
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%shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
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%B = shl i32 %A, %shift.upgrd.1 ; <i32> [#uses=1]
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%Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
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%shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
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%C = lshr i32 %A, %shift.upgrd.2 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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; 32-LABEL: rotl32:
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; 32: # BB#0:
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; 32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; 32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-NEXT: roll %cl, %eax
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; 32-NEXT: retl
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;
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; 64-LABEL: rotl32:
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; 64: # BB#0:
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; 64-NEXT: movl %esi, %ecx
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; 64-NEXT: roll %cl, %edi
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; 64-NEXT: movl %edi, %eax
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; 64-NEXT: retq
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%shift.upgrd.1 = zext i8 %Amt to i32
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%B = shl i32 %A, %shift.upgrd.1
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%Amt2 = sub i8 32, %Amt
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%shift.upgrd.2 = zext i8 %Amt2 to i32
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%C = lshr i32 %A, %shift.upgrd.2
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%D = or i32 %B, %C
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ret i32 %D
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}
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define i32 @rotr32(i32 %A, i8 %Amt) {
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%shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
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%B = lshr i32 %A, %shift.upgrd.3 ; <i32> [#uses=1]
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%Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
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%shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
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%C = shl i32 %A, %shift.upgrd.4 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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; 32-LABEL: rotr32:
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; 32: # BB#0:
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; 32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; 32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-NEXT: rorl %cl, %eax
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; 32-NEXT: retl
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;
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; 64-LABEL: rotr32:
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; 64: # BB#0:
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; 64-NEXT: movl %esi, %ecx
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; 64-NEXT: rorl %cl, %edi
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; 64-NEXT: movl %edi, %eax
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; 64-NEXT: retq
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%shift.upgrd.3 = zext i8 %Amt to i32
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%B = lshr i32 %A, %shift.upgrd.3
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%Amt2 = sub i8 32, %Amt
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%shift.upgrd.4 = zext i8 %Amt2 to i32
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%C = shl i32 %A, %shift.upgrd.4
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%D = or i32 %B, %C
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ret i32 %D
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}
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define i32 @rotli32(i32 %A) {
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%B = shl i32 %A, 5 ; <i32> [#uses=1]
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%C = lshr i32 %A, 27 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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; 32-LABEL: rotli32:
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; 32: # BB#0:
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; 32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-NEXT: roll $5, %eax
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; 32-NEXT: retl
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;
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; 64-LABEL: rotli32:
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; 64: # BB#0:
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; 64-NEXT: roll $5, %edi
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; 64-NEXT: movl %edi, %eax
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; 64-NEXT: retq
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%B = shl i32 %A, 5
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%C = lshr i32 %A, 27
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%D = or i32 %B, %C
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ret i32 %D
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}
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define i32 @rotri32(i32 %A) {
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%B = lshr i32 %A, 5 ; <i32> [#uses=1]
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%C = shl i32 %A, 27 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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; 32-LABEL: rotri32:
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; 32: # BB#0:
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; 32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-NEXT: roll $27, %eax
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; 32-NEXT: retl
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;
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; 64-LABEL: rotri32:
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; 64: # BB#0:
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; 64-NEXT: roll $27, %edi
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; 64-NEXT: movl %edi, %eax
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; 64-NEXT: retq
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%B = lshr i32 %A, 5
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%C = shl i32 %A, 27
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%D = or i32 %B, %C
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ret i32 %D
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}
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define i32 @rotl1_32(i32 %A) {
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; 32-LABEL: rotl1_32:
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; 32: # BB#0:
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; 32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-NEXT: roll %eax
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; 32-NEXT: retl
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;
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; 64-LABEL: rotl1_32:
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; 64: # BB#0:
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; 64-NEXT: roll %edi
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; 64-NEXT: movl %edi, %eax
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; 64-NEXT: retq
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%B = shl i32 %A, 1
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%C = lshr i32 %A, 31
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%D = or i32 %B, %C
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ret i32 %D
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}
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define i32 @rotr1_32(i32 %A) {
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; 32-LABEL: rotr1_32:
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; 32: # BB#0:
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; 32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-NEXT: roll $31, %eax
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; 32-NEXT: retl
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;
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; 64-LABEL: rotr1_32:
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; 64: # BB#0:
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; 64-NEXT: roll $31, %edi
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; 64-NEXT: movl %edi, %eax
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; 64-NEXT: retq
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%B = shl i32 %A, 31
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%C = lshr i32 %A, 1
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%D = or i32 %B, %C
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ret i32 %D
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}
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define i16 @rotl16(i16 %A, i8 %Amt) {
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%shift.upgrd.5 = zext i8 %Amt to i16 ; <i16> [#uses=1]
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%B = shl i16 %A, %shift.upgrd.5 ; <i16> [#uses=1]
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%Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
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%shift.upgrd.6 = zext i8 %Amt2 to i16 ; <i16> [#uses=1]
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%C = lshr i16 %A, %shift.upgrd.6 ; <i16> [#uses=1]
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%D = or i16 %B, %C ; <i16> [#uses=1]
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; 32-LABEL: rotl16:
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; 32: # BB#0:
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; 32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; 32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; 32-NEXT: rolw %cl, %ax
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; 32-NEXT: retl
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;
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; 64-LABEL: rotl16:
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; 64: # BB#0:
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; 64-NEXT: movl %esi, %ecx
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; 64-NEXT: rolw %cl, %di
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; 64-NEXT: movl %edi, %eax
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; 64-NEXT: retq
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%shift.upgrd.5 = zext i8 %Amt to i16
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%B = shl i16 %A, %shift.upgrd.5
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%Amt2 = sub i8 16, %Amt
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%shift.upgrd.6 = zext i8 %Amt2 to i16
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%C = lshr i16 %A, %shift.upgrd.6
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%D = or i16 %B, %C
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ret i16 %D
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||||
}
|
||||
|
||||
define i16 @rotr16(i16 %A, i8 %Amt) {
|
||||
%shift.upgrd.7 = zext i8 %Amt to i16 ; <i16> [#uses=1]
|
||||
%B = lshr i16 %A, %shift.upgrd.7 ; <i16> [#uses=1]
|
||||
%Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
|
||||
%shift.upgrd.8 = zext i8 %Amt2 to i16 ; <i16> [#uses=1]
|
||||
%C = shl i16 %A, %shift.upgrd.8 ; <i16> [#uses=1]
|
||||
%D = or i16 %B, %C ; <i16> [#uses=1]
|
||||
; 32-LABEL: rotr16:
|
||||
; 32: # BB#0:
|
||||
; 32-NEXT: movb {{[0-9]+}}(%esp), %cl
|
||||
; 32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
||||
; 32-NEXT: rorw %cl, %ax
|
||||
; 32-NEXT: retl
|
||||
;
|
||||
; 64-LABEL: rotr16:
|
||||
; 64: # BB#0:
|
||||
; 64-NEXT: movl %esi, %ecx
|
||||
; 64-NEXT: rorw %cl, %di
|
||||
; 64-NEXT: movl %edi, %eax
|
||||
; 64-NEXT: retq
|
||||
%shift.upgrd.7 = zext i8 %Amt to i16
|
||||
%B = lshr i16 %A, %shift.upgrd.7
|
||||
%Amt2 = sub i8 16, %Amt
|
||||
%shift.upgrd.8 = zext i8 %Amt2 to i16
|
||||
%C = shl i16 %A, %shift.upgrd.8
|
||||
%D = or i16 %B, %C
|
||||
ret i16 %D
|
||||
}
|
||||
|
||||
define i16 @rotli16(i16 %A) {
|
||||
%B = shl i16 %A, 5 ; <i16> [#uses=1]
|
||||
%C = lshr i16 %A, 11 ; <i16> [#uses=1]
|
||||
%D = or i16 %B, %C ; <i16> [#uses=1]
|
||||
; 32-LABEL: rotli16:
|
||||
; 32: # BB#0:
|
||||
; 32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
||||
; 32-NEXT: rolw $5, %ax
|
||||
; 32-NEXT: retl
|
||||
;
|
||||
; 64-LABEL: rotli16:
|
||||
; 64: # BB#0:
|
||||
; 64-NEXT: rolw $5, %di
|
||||
; 64-NEXT: movl %edi, %eax
|
||||
; 64-NEXT: retq
|
||||
%B = shl i16 %A, 5
|
||||
%C = lshr i16 %A, 11
|
||||
%D = or i16 %B, %C
|
||||
ret i16 %D
|
||||
}
|
||||
|
||||
define i16 @rotri16(i16 %A) {
|
||||
%B = lshr i16 %A, 5 ; <i16> [#uses=1]
|
||||
%C = shl i16 %A, 11 ; <i16> [#uses=1]
|
||||
%D = or i16 %B, %C ; <i16> [#uses=1]
|
||||
; 32-LABEL: rotri16:
|
||||
; 32: # BB#0:
|
||||
; 32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
||||
; 32-NEXT: rolw $11, %ax
|
||||
; 32-NEXT: retl
|
||||
;
|
||||
; 64-LABEL: rotri16:
|
||||
; 64: # BB#0:
|
||||
; 64-NEXT: rolw $11, %di
|
||||
; 64-NEXT: movl %edi, %eax
|
||||
; 64-NEXT: retq
|
||||
%B = lshr i16 %A, 5
|
||||
%C = shl i16 %A, 11
|
||||
%D = or i16 %B, %C
|
||||
ret i16 %D
|
||||
}
|
||||
|
||||
define i16 @rotl1_16(i16 %A) {
|
||||
; 32-LABEL: rotl1_16:
|
||||
; 32: # BB#0:
|
||||
; 32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
||||
; 32-NEXT: rolw %ax
|
||||
; 32-NEXT: retl
|
||||
;
|
||||
; 64-LABEL: rotl1_16:
|
||||
; 64: # BB#0:
|
||||
; 64-NEXT: rolw %di
|
||||
; 64-NEXT: movl %edi, %eax
|
||||
; 64-NEXT: retq
|
||||
%B = shl i16 %A, 1
|
||||
%C = lshr i16 %A, 15
|
||||
%D = or i16 %B, %C
|
||||
ret i16 %D
|
||||
}
|
||||
|
||||
define i16 @rotr1_16(i16 %A) {
|
||||
; 32-LABEL: rotr1_16:
|
||||
; 32: # BB#0:
|
||||
; 32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
||||
; 32-NEXT: rolw $15, %ax
|
||||
; 32-NEXT: retl
|
||||
;
|
||||
; 64-LABEL: rotr1_16:
|
||||
; 64: # BB#0:
|
||||
; 64-NEXT: rolw $15, %di
|
||||
; 64-NEXT: movl %edi, %eax
|
||||
; 64-NEXT: retq
|
||||
%B = lshr i16 %A, 1
|
||||
%C = shl i16 %A, 15
|
||||
%D = or i16 %B, %C
|
||||
ret i16 %D
|
||||
}
|
||||
|
||||
define i8 @rotl8(i8 %A, i8 %Amt) {
|
||||
%B = shl i8 %A, %Amt ; <i8> [#uses=1]
|
||||
%Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
|
||||
%C = lshr i8 %A, %Amt2 ; <i8> [#uses=1]
|
||||
%D = or i8 %B, %C ; <i8> [#uses=1]
|
||||
; 32-LABEL: rotl8:
|
||||
; 32: # BB#0:
|
||||
; 32-NEXT: movb {{[0-9]+}}(%esp), %cl
|
||||
; 32-NEXT: movb {{[0-9]+}}(%esp), %al
|
||||
; 32-NEXT: rolb %cl, %al
|
||||
; 32-NEXT: retl
|
||||
;
|
||||
; 64-LABEL: rotl8:
|
||||
; 64: # BB#0:
|
||||
; 64-NEXT: movl %esi, %ecx
|
||||
; 64-NEXT: rolb %cl, %dil
|
||||
; 64-NEXT: movl %edi, %eax
|
||||
; 64-NEXT: retq
|
||||
%B = shl i8 %A, %Amt
|
||||
%Amt2 = sub i8 8, %Amt
|
||||
%C = lshr i8 %A, %Amt2
|
||||
%D = or i8 %B, %C
|
||||
ret i8 %D
|
||||
}
|
||||
|
||||
define i8 @rotr8(i8 %A, i8 %Amt) {
|
||||
%B = lshr i8 %A, %Amt ; <i8> [#uses=1]
|
||||
%Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
|
||||
%C = shl i8 %A, %Amt2 ; <i8> [#uses=1]
|
||||
%D = or i8 %B, %C ; <i8> [#uses=1]
|
||||
; 32-LABEL: rotr8:
|
||||
; 32: # BB#0:
|
||||
; 32-NEXT: movb {{[0-9]+}}(%esp), %cl
|
||||
; 32-NEXT: movb {{[0-9]+}}(%esp), %al
|
||||
; 32-NEXT: rorb %cl, %al
|
||||
; 32-NEXT: retl
|
||||
;
|
||||
; 64-LABEL: rotr8:
|
||||
; 64: # BB#0:
|
||||
; 64-NEXT: movl %esi, %ecx
|
||||
; 64-NEXT: rorb %cl, %dil
|
||||
; 64-NEXT: movl %edi, %eax
|
||||
; 64-NEXT: retq
|
||||
%B = lshr i8 %A, %Amt
|
||||
%Amt2 = sub i8 8, %Amt
|
||||
%C = shl i8 %A, %Amt2
|
||||
%D = or i8 %B, %C
|
||||
ret i8 %D
|
||||
}
|
||||
|
||||
define i8 @rotli8(i8 %A) {
|
||||
%B = shl i8 %A, 5 ; <i8> [#uses=1]
|
||||
%C = lshr i8 %A, 3 ; <i8> [#uses=1]
|
||||
%D = or i8 %B, %C ; <i8> [#uses=1]
|
||||
; 32-LABEL: rotli8:
|
||||
; 32: # BB#0:
|
||||
; 32-NEXT: movb {{[0-9]+}}(%esp), %al
|
||||
; 32-NEXT: rolb $5, %al
|
||||
; 32-NEXT: retl
|
||||
;
|
||||
; 64-LABEL: rotli8:
|
||||
; 64: # BB#0:
|
||||
; 64-NEXT: rolb $5, %dil
|
||||
; 64-NEXT: movl %edi, %eax
|
||||
; 64-NEXT: retq
|
||||
%B = shl i8 %A, 5
|
||||
%C = lshr i8 %A, 3
|
||||
%D = or i8 %B, %C
|
||||
ret i8 %D
|
||||
}
|
||||
|
||||
define i8 @rotri8(i8 %A) {
|
||||
%B = lshr i8 %A, 5 ; <i8> [#uses=1]
|
||||
%C = shl i8 %A, 3 ; <i8> [#uses=1]
|
||||
%D = or i8 %B, %C ; <i8> [#uses=1]
|
||||
; 32-LABEL: rotri8:
|
||||
; 32: # BB#0:
|
||||
; 32-NEXT: movb {{[0-9]+}}(%esp), %al
|
||||
; 32-NEXT: rolb $3, %al
|
||||
; 32-NEXT: retl
|
||||
;
|
||||
; 64-LABEL: rotri8:
|
||||
; 64: # BB#0:
|
||||
; 64-NEXT: rolb $3, %dil
|
||||
; 64-NEXT: movl %edi, %eax
|
||||
; 64-NEXT: retq
|
||||
%B = lshr i8 %A, 5
|
||||
%C = shl i8 %A, 3
|
||||
%D = or i8 %B, %C
|
||||
ret i8 %D
|
||||
}
|
||||
|
||||
define i8 @rotl1_8(i8 %A) {
|
||||
; 32-LABEL: rotl1_8:
|
||||
; 32: # BB#0:
|
||||
; 32-NEXT: movb {{[0-9]+}}(%esp), %al
|
||||
; 32-NEXT: rolb %al
|
||||
; 32-NEXT: retl
|
||||
;
|
||||
; 64-LABEL: rotl1_8:
|
||||
; 64: # BB#0:
|
||||
; 64-NEXT: rolb %dil
|
||||
; 64-NEXT: movl %edi, %eax
|
||||
; 64-NEXT: retq
|
||||
%B = shl i8 %A, 1
|
||||
%C = lshr i8 %A, 7
|
||||
%D = or i8 %B, %C
|
||||
ret i8 %D
|
||||
}
|
||||
|
||||
define i8 @rotr1_8(i8 %A) {
|
||||
; 32-LABEL: rotr1_8:
|
||||
; 32: # BB#0:
|
||||
; 32-NEXT: movb {{[0-9]+}}(%esp), %al
|
||||
; 32-NEXT: rolb $7, %al
|
||||
; 32-NEXT: retl
|
||||
;
|
||||
; 64-LABEL: rotr1_8:
|
||||
; 64: # BB#0:
|
||||
; 64-NEXT: rolb $7, %dil
|
||||
; 64-NEXT: movl %edi, %eax
|
||||
; 64-NEXT: retq
|
||||
%B = lshr i8 %A, 1
|
||||
%C = shl i8 %A, 7
|
||||
%D = or i8 %B, %C
|
||||
ret i8 %D
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue