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ARM: partially handle 32-bit relocations for WoA 

IMAGE_REL_ARM_MOV32T relocations require that the movw/movt pair-wise
relocation is not split up and reordered. When expanding the mov32imm
pseudo-instruction, create a bundle if the machine operand is referencing an
address.  This helps ensure that the relocatable address load is not reordered
by subsequent passes.

Unfortunately, this only partially handles the case as the Constant Island Pass
occurs after the instructions are unbundled and does not properly handle
bundles.  That is a more fundamental issue with the pass itself and beyond the
scope of this change.

llvm-svn: 207608
This commit is contained in:
Saleem Abdulrasool 2014-04-30 04:54:58 +00:00
parent ae360dc36c
commit f8222631a5
2 changed files with 72 additions and 0 deletions
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45
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -615,6 +615,39 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
MI.eraseFromParent();
}
static bool IsAnAddressOperand(const MachineOperand &MO) {
// This check is overly conservative. Unless we are certain that the machine
// operand is not a symbol reference, we return that it is a symbol reference.
// This is important as the load pair may not be split up Windows.
switch (MO.getType()) {
default: llvm_unreachable("unhandled machine operand type");
case MachineOperand::MO_Register:
case MachineOperand::MO_Immediate:
case MachineOperand::MO_CImmediate:
case MachineOperand::MO_FPImmediate:
return false;
case MachineOperand::MO_MachineBasicBlock:
return true;
case MachineOperand::MO_FrameIndex:
return false;
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_TargetIndex:
case MachineOperand::MO_JumpTableIndex:
case MachineOperand::MO_ExternalSymbol:
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_BlockAddress:
return true;
case MachineOperand::MO_RegisterMask:
case MachineOperand::MO_RegisterLiveOut:
return false;
case MachineOperand::MO_Metadata:
case MachineOperand::MO_MCSymbol:
return true;
case MachineOperand::MO_CFIIndex:
return false;
}
}
void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI) {
MachineInstr &MI = *MBBI;
@ -625,10 +658,14 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
bool DstIsDead = MI.getOperand(0).isDead();
bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
MachineInstrBuilder LO16, HI16;
if (!STI->hasV6T2Ops() &&
(Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
// FIXME Windows CE supports older ARM CPUs
assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
// Expand into a movi + orr.
LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
@ -660,6 +697,9 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
HI16Opc = ARM::MOVTi16;
}
if (RequiresBundling)
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(TargetOpcode::BUNDLE));
LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
@ -683,6 +723,11 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
LO16.addImm(Pred).addReg(PredReg);
HI16.addImm(Pred).addReg(PredReg);
if (RequiresBundling) {
LO16->bundleWithPred();
HI16->bundleWithPred();
}
TransferImpOps(MI, LO16, HI16);
MI.eraseFromParent();
}

27
llvm/test/CodeGen/ARM/Windows/movw-movt-relocations.ll Normal file
View File

@ -0,0 +1,27 @@
; RUN: llc -mtriple=thumbv7-windows -o - %s \
; RUN: | FileCheck %s -check-prefix CHECK-WINDOWS
; RUN: llc -mtriple=thumbv7-eabi -o - %s \
; RUN: | FileCheck %s -check-prefix CHECK-EABI
@i = common global i32 0, align 4
@j = common global i32 0, align 4
; Function Attrs: nounwind optsize readonly
define i32 @relocation(i32 %j, i32 %k) {
entry:
%0 = load i32* @i, align 4
%1 = load i32* @j, align 4
%add = add nsw i32 %1, %0
ret i32 %add
}
; CHECK-WINDOWS: movw r[[i:[0-4]]], :lower16:i
; CHECK-WINDOWS-NEXT: movt r[[i]], :upper16:i
; CHECK-WINDOWS: movw r[[j:[0-4]]], :lower16:j
; CHECK-WINDOWS-NEXT: movt r[[j]], :upper16:j
; CHECK-EABI: movw r[[i:[0-4]]], :lower16:i
; CHECK-EABI: movw r[[j:[0-4]]], :lower16:j
; CHECK-EABI-NEXT: movt r[[i]], :upper16:i
; CHECK-EABI-NEXT: movt r[[j]], :upper16:j