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[AArch64] Add patterns to fold zext(cmpeq(x, splat(0))) 

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D129626
This commit is contained in:
Cullen Rhodes 2022-07-19 07:51:28 +00:00
parent 4bb19de4b6
commit f7b2d4aac6
2 changed files with 14 additions and 8 deletions
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10
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
View File

@ -455,6 +455,16 @@ let Predicates = [HasSVEorSME] in {
defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs", AArch64fabs_mt>;
defm FNEG_ZPmZ : sve_int_un_pred_arit_1_fp<0b101, "fneg", AArch64fneg_mt>;
// zext(cmpeq(x, splat(0))) -> cnot(x)
def : Pat<(nxv16i8 (zext (nxv16i1 (AArch64setcc_z (nxv16i1 (SVEAllActive):$Pg), nxv16i8:$Op2, (SVEDup0), SETEQ)))),
(CNOT_ZPmZ_B $Op2, $Pg, $Op2)>;
def : Pat<(nxv8i16 (zext (nxv8i1 (AArch64setcc_z (nxv8i1 (SVEAllActive):$Pg), nxv8i16:$Op2, (SVEDup0), SETEQ)))),
(CNOT_ZPmZ_H $Op2, $Pg, $Op2)>;
def : Pat<(nxv4i32 (zext (nxv4i1 (AArch64setcc_z (nxv4i1 (SVEAllActive):$Pg), nxv4i32:$Op2, (SVEDup0), SETEQ)))),
(CNOT_ZPmZ_S $Op2, $Pg, $Op2)>;
def : Pat<(nxv2i64 (zext (nxv2i1 (AArch64setcc_z (nxv2i1 (SVEAllActive):$Pg), nxv2i64:$Op2, (SVEDup0), SETEQ)))),
(CNOT_ZPmZ_D $Op2, $Pg, $Op2)>;
defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax", "SMAX_ZPZZ", int_aarch64_sve_smax, DestructiveBinaryComm>;
defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax", "UMAX_ZPZZ", int_aarch64_sve_umax, DestructiveBinaryComm>;
defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin", "SMIN_ZPZZ", int_aarch64_sve_smin, DestructiveBinaryComm>;

12
llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
View File

@ -57,8 +57,7 @@ define <vscale x 16 x i8> @icmp_cnot_nxv16i8(<vscale x 16 x i8> %a) {
; CHECK-LABEL: icmp_cnot_nxv16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: mov z0.b, p0/z, #1 // =0x1
; CHECK-NEXT: cnot z0.b, p0/m, z0.b
; CHECK-NEXT: ret
%mask = icmp eq <vscale x 16 x i8> %a, zeroinitializer
%zext = zext <vscale x 16 x i1> %mask to <vscale x 16 x i8>
@ -69,8 +68,7 @@ define <vscale x 8 x i16> @icmp_cnot_nxv8i16(<vscale x 8 x i16> %a) {
; CHECK-LABEL: icmp_cnot_nxv8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
; CHECK-NEXT: mov z0.h, p0/z, #1 // =0x1
; CHECK-NEXT: cnot z0.h, p0/m, z0.h
; CHECK-NEXT: ret
%mask = icmp eq <vscale x 8 x i16> %a, zeroinitializer
%zext = zext <vscale x 8 x i1> %mask to <vscale x 8 x i16>
@ -81,8 +79,7 @@ define <vscale x 4 x i32> @icmp_cnot_nxv4i32(<vscale x 4 x i32> %a) {
; CHECK-LABEL: icmp_cnot_nxv4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
; CHECK-NEXT: mov z0.s, p0/z, #1 // =0x1
; CHECK-NEXT: cnot z0.s, p0/m, z0.s
; CHECK-NEXT: ret
%mask = icmp eq <vscale x 4 x i32> %a, zeroinitializer
%zext = zext <vscale x 4 x i1> %mask to <vscale x 4 x i32>
@ -93,8 +90,7 @@ define <vscale x 2 x i64> @icmp_cnot_nxv2i64(<vscale x 2 x i64> %a) {
; CHECK-LABEL: icmp_cnot_nxv2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #0
; CHECK-NEXT: mov z0.d, p0/z, #1 // =0x1
; CHECK-NEXT: cnot z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%mask = icmp eq <vscale x 2 x i64> %a, zeroinitializer
%zext = zext <vscale x 2 x i1> %mask to <vscale x 2 x i64>