forked from OSchip/llvm-project
[X86] Add AVX512 load opcodes and a couple AVX load opcodes to X86InstrInfo::areLoadsFromSameBasePtr.
llvm-svn: 275765
This commit is contained in:
Craig Topper
parent
650a15e2b3
commit
f7a06c29bc
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@ -6728,6 +6728,7 @@ X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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case X86::MOVAPSrm:
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case X86::MOVUPSrm:
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case X86::MOVAPDrm:
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case X86::MOVUPDrm:
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case X86::MOVDQArm:
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case X86::MOVDQUrm:
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// AVX load instructions
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@ -6738,13 +6739,52 @@ X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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case X86::VMOVAPSrm:
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case X86::VMOVUPSrm:
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case X86::VMOVAPDrm:
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case X86::VMOVUPDrm:
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case X86::VMOVDQArm:
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case X86::VMOVDQUrm:
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case X86::VMOVAPSYrm:
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case X86::VMOVUPSYrm:
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case X86::VMOVAPDYrm:
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case X86::VMOVUPDYrm:
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case X86::VMOVDQAYrm:
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case X86::VMOVDQUYrm:
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// AVX512 load instructions
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case X86::VMOVSSZrm:
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case X86::VMOVSDZrm:
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case X86::VMOVAPSZ128rm:
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case X86::VMOVUPSZ128rm:
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case X86::VMOVAPDZ128rm:
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case X86::VMOVUPDZ128rm:
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case X86::VMOVDQU8Z128rm:
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case X86::VMOVDQU16Z128rm:
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case X86::VMOVDQA32Z128rm:
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case X86::VMOVDQU32Z128rm:
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case X86::VMOVDQA64Z128rm:
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case X86::VMOVDQU64Z128rm:
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case X86::VMOVAPSZ256rm:
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case X86::VMOVUPSZ256rm:
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case X86::VMOVAPDZ256rm:
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case X86::VMOVUPDZ256rm:
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case X86::VMOVDQU8Z256rm:
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case X86::VMOVDQU16Z256rm:
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case X86::VMOVDQA32Z256rm:
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case X86::VMOVDQU32Z256rm:
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case X86::VMOVDQA64Z256rm:
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case X86::VMOVDQU64Z256rm:
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case X86::VMOVAPSZrm:
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case X86::VMOVUPSZrm:
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case X86::VMOVAPDZrm:
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case X86::VMOVUPDZrm:
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case X86::VMOVDQU8Zrm:
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case X86::VMOVDQU16Zrm:
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case X86::VMOVDQA32Zrm:
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case X86::VMOVDQU32Zrm:
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case X86::VMOVDQA64Zrm:
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case X86::VMOVDQU64Zrm:
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case X86::KMOVBkm:
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case X86::KMOVWkm:
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case X86::KMOVDkm:
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case X86::KMOVQkm:
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break;
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}
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switch (Opc2) {
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@ -6765,6 +6805,7 @@ X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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case X86::MOVAPSrm:
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case X86::MOVUPSrm:
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case X86::MOVAPDrm:
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case X86::MOVUPDrm:
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case X86::MOVDQArm:
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case X86::MOVDQUrm:
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// AVX load instructions
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@ -6775,13 +6816,52 @@ X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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case X86::VMOVAPSrm:
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case X86::VMOVUPSrm:
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case X86::VMOVAPDrm:
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case X86::VMOVUPDrm:
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case X86::VMOVDQArm:
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case X86::VMOVDQUrm:
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case X86::VMOVAPSYrm:
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case X86::VMOVUPSYrm:
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case X86::VMOVAPDYrm:
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case X86::VMOVUPDYrm:
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case X86::VMOVDQAYrm:
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case X86::VMOVDQUYrm:
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// AVX512 load instructions
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case X86::VMOVSSZrm:
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case X86::VMOVSDZrm:
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case X86::VMOVAPSZ128rm:
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case X86::VMOVUPSZ128rm:
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case X86::VMOVAPDZ128rm:
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case X86::VMOVUPDZ128rm:
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case X86::VMOVDQU8Z128rm:
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case X86::VMOVDQU16Z128rm:
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case X86::VMOVDQA32Z128rm:
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case X86::VMOVDQU32Z128rm:
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case X86::VMOVDQA64Z128rm:
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case X86::VMOVDQU64Z128rm:
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case X86::VMOVAPSZ256rm:
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case X86::VMOVUPSZ256rm:
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case X86::VMOVAPDZ256rm:
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case X86::VMOVUPDZ256rm:
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case X86::VMOVDQU8Z256rm:
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case X86::VMOVDQU16Z256rm:
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case X86::VMOVDQA32Z256rm:
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case X86::VMOVDQU32Z256rm:
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case X86::VMOVDQA64Z256rm:
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case X86::VMOVDQU64Z256rm:
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case X86::VMOVAPSZrm:
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case X86::VMOVUPSZrm:
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case X86::VMOVAPDZrm:
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case X86::VMOVUPDZrm:
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case X86::VMOVDQU8Zrm:
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case X86::VMOVDQU16Zrm:
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case X86::VMOVDQA32Zrm:
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case X86::VMOVDQU32Zrm:
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case X86::VMOVDQA64Zrm:
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case X86::VMOVDQU64Zrm:
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case X86::KMOVBkm:
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case X86::KMOVWkm:
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case X86::KMOVDkm:
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case X86::KMOVQkm:
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break;
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}
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@ -517,20 +517,20 @@ define <64 x i8> @test16(i64 %x) {
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; KNL-NEXT: movl %edi, {{[0-9]+}}(%rsp)
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; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
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; KNL-NEXT: kmovw (%rsp), %k1
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; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
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; KNL-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1} {z}
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; KNL-NEXT: vpmovdb %zmm1, %xmm1
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; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
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; KNL-NEXT: vmovdqa32 %zmm0, %zmm2 {%k1} {z}
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; KNL-NEXT: vmovdqa32 %zmm0, %zmm2 {%k2} {z}
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; KNL-NEXT: vpmovdb %zmm2, %xmm2
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; KNL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm2
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; KNL-NEXT: movl $1, %eax
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; KNL-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1
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; KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm1[0,1,2,3],ymm2[4,5,6,7]
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; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
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; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
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; KNL-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1} {z}
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; KNL-NEXT: vpmovdb %zmm1, %xmm1
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; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
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; KNL-NEXT: vmovdqa32 %zmm0, %zmm0 {%k1} {z}
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; KNL-NEXT: vmovdqa32 %zmm0, %zmm0 {%k2} {z}
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; KNL-NEXT: vpmovdb %zmm0, %xmm0
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; KNL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1
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; KNL-NEXT: vpsllw $7, %ymm2, %ymm0
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@ -575,10 +575,10 @@ define <64 x i8> @test17(i64 %x, i32 %y, i32 %z) {
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; KNL-NEXT: movl %edi, {{[0-9]+}}(%rsp)
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; KNL-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1
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; KNL-NEXT: kmovw (%rsp), %k1
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; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} {z}
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; KNL-NEXT: vpmovdb %zmm0, %xmm0
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; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm2 {%k1} {z}
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm2 {%k2} {z}
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; KNL-NEXT: vpmovdb %zmm2, %xmm2
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; KNL-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
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; KNL-NEXT: xorl %eax, %eax
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@ -591,10 +591,10 @@ define <64 x i8> @test17(i64 %x, i32 %y, i32 %z) {
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; KNL-NEXT: vpxor %ymm2, %ymm2, %ymm2
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; KNL-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0
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; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
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; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm2 {%k1} {z}
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; KNL-NEXT: vpmovdb %zmm2, %xmm2
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; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm1 {%k1} {z}
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm1 {%k2} {z}
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; KNL-NEXT: vpmovdb %zmm1, %xmm1
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; KNL-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
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; KNL-NEXT: movq %rbp, %rsp
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@ -1319,10 +1319,10 @@ define void @ktest_2(<32 x float> %in, float * %base) {
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;
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; SKX-LABEL: ktest_2:
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; SKX: ## BB#0:
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; SKX-NEXT: vmovups 64(%rdi), %zmm2
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; SKX-NEXT: vmovups (%rdi), %zmm3
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; SKX-NEXT: vcmpltps %zmm0, %zmm3, %k1
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; SKX-NEXT: vcmpltps %zmm1, %zmm2, %k2
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; SKX-NEXT: vmovups (%rdi), %zmm2
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; SKX-NEXT: vmovups 64(%rdi), %zmm3
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; SKX-NEXT: vcmpltps %zmm0, %zmm2, %k1
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; SKX-NEXT: vcmpltps %zmm1, %zmm3, %k2
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; SKX-NEXT: kunpckwd %k1, %k2, %k0
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; SKX-NEXT: vmovups 68(%rdi), %zmm2 {%k2} {z}
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; SKX-NEXT: vmovups 4(%rdi), %zmm3 {%k1} {z}
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@ -1449,11 +1449,11 @@ define <32 x i16> @load_32i1(<32 x i1>* %a) {
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; KNL-LABEL: load_32i1:
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; KNL: ## BB#0:
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; KNL-NEXT: kmovw (%rdi), %k1
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; KNL-NEXT: kmovw 2(%rdi), %k2
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; KNL-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} {z}
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; KNL-NEXT: vpmovdw %zmm0, %ymm0
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; KNL-NEXT: kmovw 2(%rdi), %k1
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm1 {%k1} {z}
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm1 {%k2} {z}
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; KNL-NEXT: vpmovdw %zmm1, %ymm1
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; KNL-NEXT: retq
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;
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@ -1471,18 +1471,18 @@ define <64 x i8> @load_64i1(<64 x i1>* %a) {
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; KNL-LABEL: load_64i1:
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; KNL: ## BB#0:
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; KNL-NEXT: kmovw (%rdi), %k1
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; KNL-NEXT: kmovw 2(%rdi), %k2
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; KNL-NEXT: kmovw 4(%rdi), %k3
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; KNL-NEXT: kmovw 6(%rdi), %k4
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; KNL-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} {z}
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; KNL-NEXT: vpmovdb %zmm0, %xmm0
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; KNL-NEXT: kmovw 2(%rdi), %k1
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm2 {%k1} {z}
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm2 {%k2} {z}
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; KNL-NEXT: vpmovdb %zmm2, %xmm2
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; KNL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; KNL-NEXT: kmovw 4(%rdi), %k1
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm2 {%k1} {z}
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm2 {%k3} {z}
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; KNL-NEXT: vpmovdb %zmm2, %xmm2
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; KNL-NEXT: kmovw 6(%rdi), %k1
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm1 {%k1} {z}
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; KNL-NEXT: vmovdqa32 %zmm1, %zmm1 {%k4} {z}
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; KNL-NEXT: vpmovdb %zmm1, %xmm1
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; KNL-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
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; KNL-NEXT: retq
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@ -3738,11 +3738,11 @@ define <32 x i8> @load_sext_32i1_to_32i8(<32 x i1> *%ptr) nounwind readnone {
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; AVX512-LABEL: load_sext_32i1_to_32i8:
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; AVX512: # BB#0: # %entry
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; AVX512-NEXT: kmovw (%rdi), %k1
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; AVX512-NEXT: kmovw 2(%rdi), %k2
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; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
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; AVX512-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1} {z}
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; AVX512-NEXT: vpmovdb %zmm1, %xmm1
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; AVX512-NEXT: kmovw 2(%rdi), %k1
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; AVX512-NEXT: vmovdqa32 %zmm0, %zmm0 {%k1} {z}
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; AVX512-NEXT: vmovdqa32 %zmm0, %zmm0 {%k2} {z}
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; AVX512-NEXT: vpmovdb %zmm0, %xmm0
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; AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX512-NEXT: retq
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