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Revert "[mips] Honour -mno-odd-spreg for vector splat" 

This reverts commit r291556. It was a mixture of two differentials and
was missing a test.

llvm-svn: 291562
This commit is contained in:
Simon Dardis 2017-01-10 13:57:44 +00:00
parent 0f0407331e
commit f790ff3da0
2 changed files with 2 additions and 18 deletions
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12
llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
View File

@ -11,7 +11,6 @@
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/MipsABIInfo.h"
#include "MipsTargetStreamer.h"
#include "InstPrinter/MipsInstPrinter.h"
#include "MipsELFStreamer.h"
@ -686,17 +685,6 @@ MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
// issues as well.
unsigned EFlags = MCA.getELFHeaderEFlags();
// FIXME: Fix a dependency issue by instantiating the ABI object to some
// default based off the triple. The triple doesn't describe the target
// fully, but any external user of the API that uses the MCTargetStreamer
// would otherwise crash on assertion failure.
ABI = MipsABIInfo(
STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
STI.getTargetTriple().getArch() == Triple::ArchType::mips
? MipsABIInfo::O32()
: MipsABIInfo::N64());
// Architecture
if (Features[Mips::FeatureMips64r6])
EFlags |= ELF::EF_MIPS_ARCH_64R6;

8
llvm/lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -3377,12 +3377,8 @@ MipsSETargetLowering::emitFILL_FW(MachineInstr &MI,
DebugLoc DL = MI.getDebugLoc();
unsigned Wd = MI.getOperand(0).getReg();
unsigned Fs = MI.getOperand(1).getReg();
unsigned Wt1 = RegInfo.createVirtualRegister(
Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
: &Mips::MSA128WEvensRegClass);
unsigned Wt2 = RegInfo.createVirtualRegister(
Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
: &Mips::MSA128WEvensRegClass);
unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)