forked from OSchip/llvm-project
[Hexagon] Add fshl/fshr -> combine() tests identified in D75114
Added tests showing that the fshl/fshr -> combine() is working the wrong way around
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@ -256,6 +256,22 @@ b0:
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ret i64 %v0
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}
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; CHECK-LABEL: f30:
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; CHECK: r[[R00:[0-9]+]] = combine(r0.h,r1.l)
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define i32 @f30(i32 %a0, i32 %a1) #1 {
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b0:
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%v0 = tail call i32 @llvm.fshl.i32(i32 %a0, i32 %a1, i32 16)
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ret i32 %v0
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}
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; CHECK-LABEL: f31:
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; CHECK: r[[R00:[0-9]+]] = combine(r0.h,r1.l)
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define i32 @f31(i32 %a0, i32 %a1) #1 {
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b0:
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%v0 = tail call i32 @llvm.fshr.i32(i32 %a0, i32 %a1, i32 16)
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ret i32 %v0
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}
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declare i32 @llvm.fshl.i32(i32, i32, i32) #0
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declare i32 @llvm.fshr.i32(i32, i32, i32) #0
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declare i64 @llvm.fshl.i64(i64, i64, i64) #0
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