forked from OSchip/llvm-project
Handle the constantfp created during post-legalization dag combiner phase.
llvm-svn: 78594
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246617857f
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@ -988,6 +988,24 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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// Other cases are autogenerated.
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break;
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}
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case ISD::ConstantFP: {
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ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(N);
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MVT VT = CFP->getValueType(0);
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ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
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SDValue CPIdx = CurDAG->getTargetConstantPool(LLVMC, TLI.getPointerTy());
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SDNode *ResNode;
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SDValue Ops[] = {
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CPIdx,
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CurDAG->getTargetConstant(0, MVT::i32),
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getAL(CurDAG),
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CurDAG->getRegister(0, MVT::i32),
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CurDAG->getEntryNode()
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};
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unsigned Opc = (VT == MVT::f32) ? ARM::FLDS : ARM::FLDD;
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ResNode=CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Ops, 5);
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ReplaceUses(Op, SDValue(ResNode, 0));
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return NULL;
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}
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case ISD::FrameIndex: {
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// Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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@ -0,0 +1,15 @@
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; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -mattr=+vfp2
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define arm_apcscc float @t1(i32 %v0) nounwind {
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entry:
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store i32 undef, i32* undef, align 4
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%0 = load [4 x i8]** undef, align 4 ; <[4 x i8]*> [#uses=1]
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%1 = load i8* undef, align 1 ; <i8> [#uses=1]
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%2 = zext i8 %1 to i32 ; <i32> [#uses=1]
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%3 = getelementptr [4 x i8]* %0, i32 %v0, i32 0 ; <i8*> [#uses=1]
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%4 = load i8* %3, align 1 ; <i8> [#uses=1]
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%5 = zext i8 %4 to i32 ; <i32> [#uses=1]
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%6 = sub i32 %5, %2 ; <i32> [#uses=1]
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%7 = sitofp i32 %6 to float ; <float> [#uses=1]
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ret float %7
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}
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