forked from OSchip/llvm-project
[LoopInterchange] Fix interchanging contents of preheader BBs
Summary: Previously LCSSA was getting broken by placing instructions into the (newly) inner *header* instead of the *pre*header. Fixes PR43474 Reviewers: fhahn Reviewed By: fhahn Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D75943
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@ -412,7 +412,6 @@ public:
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private:
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private:
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bool adjustLoopLinks();
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bool adjustLoopLinks();
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void adjustLoopPreheaders();
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bool adjustLoopBranches();
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bool adjustLoopBranches();
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Loop *OuterLoop;
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Loop *OuterLoop;
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@ -580,6 +579,12 @@ struct LoopInterchange : public LoopPass {
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LIT.transform();
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LIT.transform();
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LLVM_DEBUG(dbgs() << "Loops interchanged.\n");
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LLVM_DEBUG(dbgs() << "Loops interchanged.\n");
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LoopsInterchanged++;
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LoopsInterchanged++;
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assert(InnerLoop->isLCSSAForm(*DT) &&
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"Inner loop not left in LCSSA form after loop interchange!");
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assert(OuterLoop->isLCSSAForm(*DT) &&
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"Outer loop not left in LCSSA form after loop interchange!");
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return true;
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return true;
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}
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}
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};
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};
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@ -1319,6 +1324,23 @@ static void moveBBContents(BasicBlock *FromBB, Instruction *InsertBefore) {
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FromBB->getTerminator()->getIterator());
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FromBB->getTerminator()->getIterator());
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}
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}
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/// Swap instructions between \p BB1 and \p BB2 but keep terminators intact.
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static void swapBBContents(BasicBlock *BB1, BasicBlock *BB2) {
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// Save all non-terminator instructions of BB1 into TempInstrs and unlink them
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// from BB1 afterwards.
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auto Iter = map_range(*BB1, [](Instruction &I) { return &I; });
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SmallVector<Instruction *, 4> TempInstrs(Iter.begin(), std::prev(Iter.end()));
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for (Instruction *I : TempInstrs)
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I->removeFromParent();
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// Move instructions from BB2 to BB1.
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moveBBContents(BB2, BB1->getTerminator());
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// Move instructions from TempInstrs to BB2.
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for (Instruction *I : TempInstrs)
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I->insertBefore(BB2->getTerminator());
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}
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// Update BI to jump to NewBB instead of OldBB. Records updates to the
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// Update BI to jump to NewBB instead of OldBB. Records updates to the
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// dominator tree in DTUpdates. If \p MustUpdateOnce is true, assert that
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// dominator tree in DTUpdates. If \p MustUpdateOnce is true, assert that
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// \p OldBB is exactly once in BI's successor list.
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// \p OldBB is exactly once in BI's successor list.
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@ -1578,30 +1600,17 @@ bool LoopInterchangeTransform::adjustLoopBranches() {
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return true;
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return true;
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}
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}
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void LoopInterchangeTransform::adjustLoopPreheaders() {
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// We have interchanged the preheaders so we need to interchange the data in
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// the preheader as well.
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// This is because the content of inner preheader was previously executed
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// inside the outer loop.
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BasicBlock *OuterLoopPreHeader = OuterLoop->getLoopPreheader();
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BasicBlock *InnerLoopPreHeader = InnerLoop->getLoopPreheader();
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BasicBlock *OuterLoopHeader = OuterLoop->getHeader();
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BranchInst *InnerTermBI =
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cast<BranchInst>(InnerLoopPreHeader->getTerminator());
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// These instructions should now be executed inside the loop.
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// Move instruction into a new block after outer header.
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moveBBContents(InnerLoopPreHeader, OuterLoopHeader->getTerminator());
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// These instructions were not executed previously in the loop so move them to
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// the older inner loop preheader.
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moveBBContents(OuterLoopPreHeader, InnerTermBI);
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}
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bool LoopInterchangeTransform::adjustLoopLinks() {
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bool LoopInterchangeTransform::adjustLoopLinks() {
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// Adjust all branches in the inner and outer loop.
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// Adjust all branches in the inner and outer loop.
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bool Changed = adjustLoopBranches();
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bool Changed = adjustLoopBranches();
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if (Changed)
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if (Changed) {
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adjustLoopPreheaders();
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// We have interchanged the preheaders so we need to interchange the data in
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// the preheaders as well. This is because the content of the inner
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// preheader was previously executed inside the outer loop.
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BasicBlock *OuterLoopPreHeader = OuterLoop->getLoopPreheader();
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BasicBlock *InnerLoopPreHeader = InnerLoop->getLoopPreheader();
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swapBBContents(OuterLoopPreHeader, InnerLoopPreHeader);
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}
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return Changed;
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return Changed;
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}
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}
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@ -0,0 +1,103 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -basicaa -loop-interchange -pass-remarks-missed='loop-interchange' -verify-loop-lcssa -S | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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; void foo(int n, int m) {
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; int temp[16][16];
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; int res[16][16];
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; for(int i = 0; i < n; i++) {
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; for(int j = 0; j < m; j++)
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; res[j][i] = temp[j][i];
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; }
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; }
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define void @lcssa_08(i32 %n, i32 %m) {
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; CHECK-LABEL: @lcssa_08(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TEMP:%.*]] = alloca [16 x [16 x i32]], align 4
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; CHECK-NEXT: [[RES:%.*]] = alloca [16 x [16 x i32]], align 4
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; CHECK-NEXT: [[CMP24:%.*]] = icmp sgt i32 [[N:%.*]], 0
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; CHECK-NEXT: br i1 [[CMP24]], label [[INNER_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]
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; CHECK: outer.preheader:
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; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[M:%.*]] to i64
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; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
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; CHECK: outer.header:
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; CHECK-NEXT: [[INDVARS_IV27:%.*]] = phi i64 [ 0, [[OUTER_PREHEADER:%.*]] ], [ [[INDVARS_IV_NEXT28:%.*]], [[OUTER_LATCH:%.*]] ]
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; CHECK-NEXT: [[CMP222:%.*]] = icmp sgt i32 [[M]], 0
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; CHECK-NEXT: br i1 [[CMP222]], label [[INNER_FOR_BODY_SPLIT1:%.*]], label [[OUTER_CRIT_EDGE:%.*]]
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; CHECK: inner.preheader:
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; CHECK-NEXT: [[WIDE_TRIP_COUNT29:%.*]] = zext i32 [[N]] to i64
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; CHECK-NEXT: br label [[INNER_FOR_BODY:%.*]]
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; CHECK: inner.for.body:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[INNER_PREHEADER]] ], [ [[TMP1:%.*]], [[INNER_FOR_BODY_SPLIT:%.*]] ]
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; CHECK-NEXT: br label [[OUTER_PREHEADER]]
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; CHECK: inner.for.body.split1:
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; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [16 x [16 x i32]], [16 x [16 x i32]]* [[TEMP]], i64 0, i64 [[INDVARS_IV]], i64 [[INDVARS_IV27]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4
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; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [16 x [16 x i32]], [16 x [16 x i32]]* [[RES]], i64 0, i64 [[INDVARS_IV]], i64 [[INDVARS_IV27]]
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; CHECK-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX8]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
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; CHECK-NEXT: br label [[INNER_CRIT_EDGE:%.*]]
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; CHECK: inner.for.body.split:
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; CHECK-NEXT: [[TMP1]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], [[WIDE_TRIP_COUNT]]
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; CHECK-NEXT: br i1 [[TMP2]], label [[INNER_FOR_BODY]], label [[OUTER_CRIT_EDGE]]
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; CHECK: inner.crit_edge:
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; CHECK-NEXT: br label [[OUTER_LATCH]]
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; CHECK: outer.latch:
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; CHECK-NEXT: [[INDVARS_IV_NEXT28]] = add nuw nsw i64 [[INDVARS_IV27]], 1
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; CHECK-NEXT: [[EXITCOND30:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT28]], [[WIDE_TRIP_COUNT29]]
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; CHECK-NEXT: br i1 [[EXITCOND30]], label [[OUTER_HEADER]], label [[INNER_FOR_BODY_SPLIT]]
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; CHECK: outer.crit_edge:
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; CHECK-NEXT: br label [[FOR_COND_CLEANUP]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: ret void
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;
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entry:
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%temp = alloca [16 x [16 x i32]], align 4
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%res = alloca [16 x [16 x i32]], align 4
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%cmp24 = icmp sgt i32 %n, 0
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br i1 %cmp24, label %outer.preheader, label %for.cond.cleanup
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outer.preheader: ; preds = %entry
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%wide.trip.count29 = zext i32 %n to i64
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br label %outer.header
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outer.header: ; preds = %outer.preheader, %outer.latch
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%indvars.iv27 = phi i64 [ 0, %outer.preheader ], [ %indvars.iv.next28, %outer.latch ]
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%cmp222 = icmp sgt i32 %m, 0
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br i1 %cmp222, label %inner.preheader, label %outer.latch
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inner.preheader: ; preds = %outer.header
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; When inner.preheader becomes the outer preheader, do not move
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; %wide.trip.count into the inner loop header lest LCSSA break
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; (if %wide.trip.count gets moved, its use is now outside the inner loop).
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%wide.trip.count = zext i32 %m to i64
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br label %inner.for.body
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inner.for.body: ; preds = %inner.preheader, %inner.for.body
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%indvars.iv = phi i64 [ 0, %inner.preheader ], [ %indvars.iv.next, %inner.for.body ]
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%arrayidx6 = getelementptr inbounds [16 x [16 x i32]], [16 x [16 x i32]]* %temp, i64 0, i64 %indvars.iv, i64 %indvars.iv27
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%0 = load i32, i32* %arrayidx6, align 4
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%arrayidx8 = getelementptr inbounds [16 x [16 x i32]], [16 x [16 x i32]]* %res, i64 0, i64 %indvars.iv, i64 %indvars.iv27
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store i32 %0, i32* %arrayidx8, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp ne i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond, label %inner.for.body, label %inner.crit_edge
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inner.crit_edge: ; preds = %inner.for.body
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br label %outer.latch
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outer.latch: ; preds = %inner.crit_edge, %outer.header
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%indvars.iv.next28 = add nuw nsw i64 %indvars.iv27, 1
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%exitcond30 = icmp ne i64 %indvars.iv.next28, %wide.trip.count29
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br i1 %exitcond30, label %outer.header, label %outer.crit_edge
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outer.crit_edge: ; preds = %outer.latch
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %outer.crit_edge, %entry
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ret void
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}
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