forked from OSchip/llvm-project
[SLP]Improve/fix reordering of the gathered graph nodes.
Gathered loads/extractelements/extractvalue instructions should be checked if they can represent a vector reordering node too and their order should ve taken into account for better graph reordering analysis/ Also, if the gather node has reused scalars, they must be reordered instead of the scalars themselves. Differential Revision: https://reviews.llvm.org/D112454
This commit is contained in:
Alexey Bataev
parent
c1f3d08b06
commit
f719b794bc
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@ -766,6 +766,12 @@ public:
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/// Perform LICM and CSE on the newly generated gather sequences.
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void optimizeGatherSequence();
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/// Checks if the specified gather tree entry \p TE can be represented as a
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/// shuffled vector entry + (possibly) permutation with other gathers. It
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/// implements the checks only for possibly ordered scalars (Loads,
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/// ExtractElement, ExtractValue), which can be part of the graph.
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Optional<OrdersType> findReusedOrderedScalars(const TreeEntry &TE);
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/// Reorders the current graph to the most profitable order starting from the
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/// root node to the leaf nodes. The best order is chosen only from the nodes
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/// of the same size (vectorization factor). Smaller nodes are considered
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@ -2670,6 +2676,64 @@ static void reorderOrder(SmallVectorImpl<unsigned> &Order, ArrayRef<int> Mask) {
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fixupOrderingIndices(Order);
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}
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Optional<BoUpSLP::OrdersType>
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BoUpSLP::findReusedOrderedScalars(const BoUpSLP::TreeEntry &TE) {
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assert(TE.State == TreeEntry::NeedToGather && "Expected gather node only.");
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unsigned NumScalars = TE.Scalars.size();
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OrdersType CurrentOrder(NumScalars, NumScalars);
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SmallVector<int> Positions;
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SmallBitVector UsedPositions(NumScalars);
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const TreeEntry *STE = nullptr;
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bool IsIdentity = false;
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// Try to find all gathered scalars that are gets vectorized in other
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// vectorize node. Here we can have only one single tree vector node to
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// correctly identify order of the gathered scalars.
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for (unsigned I = 0; I < NumScalars; ++I) {
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Value *V = TE.Scalars[I];
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if (!isa<LoadInst, ExtractElementInst, ExtractValueInst>(V))
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continue;
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if (const auto *LocalSTE = getTreeEntry(V)) {
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if (!STE)
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STE = LocalSTE;
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else if (STE != LocalSTE)
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// Take the order only from the single vector node.
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return None;
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unsigned Lane =
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std::distance(STE->Scalars.begin(), find(STE->Scalars, V));
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if (Lane >= NumScalars)
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return None;
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// The partial identity (where only some elements of the gather node are
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// in the identity order) is good.
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IsIdentity |= Lane == I;
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if (CurrentOrder[Lane] != NumScalars)
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continue;
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CurrentOrder[Lane] = I;
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UsedPositions.set(I);
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}
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}
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// Need to keep the order if we have a vector entry and at least 2 scalars.
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if (STE && UsedPositions.count() > 1) {
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if (IsIdentity) {
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CurrentOrder.clear();
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return CurrentOrder;
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}
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auto *It = CurrentOrder.begin();
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for (unsigned I = 0; I < NumScalars;) {
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if (UsedPositions.test(I)) {
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++I;
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continue;
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}
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if (*It == NumScalars) {
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*It = I;
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++I;
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}
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++It;
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}
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return CurrentOrder;
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}
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return None;
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}
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void BoUpSLP::reorderTopToBottom() {
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// Maps VF to the graph nodes.
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DenseMap<unsigned, SmallPtrSet<TreeEntry *, 4>> VFToOrderedEntries;
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@ -2689,19 +2753,29 @@ void BoUpSLP::reorderTopToBottom() {
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InsertElementInst>(TE->getMainOp()) &&
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!TE->isAltShuffle()) {
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VFToOrderedEntries[TE->Scalars.size()].insert(TE.get());
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} else if (TE->State == TreeEntry::NeedToGather &&
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TE->getOpcode() == Instruction::ExtractElement &&
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!TE->isAltShuffle() &&
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isa<FixedVectorType>(cast<ExtractElementInst>(TE->getMainOp())
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->getVectorOperandType()) &&
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allSameType(TE->Scalars) && allSameBlock(TE->Scalars)) {
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// Check that gather of extractelements can be represented as
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// just a shuffle of a single vector.
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OrdersType CurrentOrder;
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bool Reuse = canReuseExtract(TE->Scalars, TE->getMainOp(), CurrentOrder);
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if (Reuse || !CurrentOrder.empty()) {
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return;
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}
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if (TE->State == TreeEntry::NeedToGather) {
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if (TE->getOpcode() == Instruction::ExtractElement &&
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!TE->isAltShuffle() &&
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isa<FixedVectorType>(cast<ExtractElementInst>(TE->getMainOp())
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->getVectorOperandType()) &&
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allSameType(TE->Scalars) && allSameBlock(TE->Scalars)) {
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// Check that gather of extractelements can be represented as
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// just a shuffle of a single vector.
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OrdersType CurrentOrder;
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bool Reuse =
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canReuseExtract(TE->Scalars, TE->getMainOp(), CurrentOrder);
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if (Reuse || !CurrentOrder.empty()) {
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VFToOrderedEntries[TE->Scalars.size()].insert(TE.get());
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GathersToOrders.try_emplace(TE.get(), CurrentOrder);
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return;
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}
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}
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if (Optional<OrdersType> CurrentOrder =
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findReusedOrderedScalars(*TE.get())) {
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VFToOrderedEntries[TE->Scalars.size()].insert(TE.get());
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GathersToOrders.try_emplace(TE.get(), CurrentOrder);
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GathersToOrders.try_emplace(TE.get(), *CurrentOrder);
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}
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}
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});
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@ -2830,6 +2904,8 @@ void BoUpSLP::reorderBottomToTop(bool IgnoreReorder) {
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for_each(VectorizableTree, [this, &OrderedEntries, &GathersToOrders,
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&NonVectorized](
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const std::unique_ptr<TreeEntry> &TE) {
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if (TE->State != TreeEntry::Vectorize)
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NonVectorized.push_back(TE.get());
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// No need to reorder if need to shuffle reuses, still need to shuffle the
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// node.
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if (!TE->ReuseShuffleIndices.empty())
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@ -2838,28 +2914,37 @@ void BoUpSLP::reorderBottomToTop(bool IgnoreReorder) {
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isa<LoadInst, ExtractElementInst, ExtractValueInst>(TE->getMainOp()) &&
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!TE->isAltShuffle()) {
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OrderedEntries.insert(TE.get());
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} else if (TE->State == TreeEntry::NeedToGather &&
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TE->getOpcode() == Instruction::ExtractElement &&
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!TE->isAltShuffle() &&
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isa<FixedVectorType>(cast<ExtractElementInst>(TE->getMainOp())
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->getVectorOperandType()) &&
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allSameType(TE->Scalars) && allSameBlock(TE->Scalars)) {
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// Check that gather of extractelements can be represented as
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// just a shuffle of a single vector with a single user only.
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OrdersType CurrentOrder;
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bool Reuse = canReuseExtract(TE->Scalars, TE->getMainOp(), CurrentOrder);
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if ((Reuse || !CurrentOrder.empty()) &&
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!any_of(
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VectorizableTree, [&TE](const std::unique_ptr<TreeEntry> &Entry) {
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return Entry->State == TreeEntry::NeedToGather &&
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Entry.get() != TE.get() && Entry->isSame(TE->Scalars);
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})) {
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return;
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}
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if (TE->State == TreeEntry::NeedToGather) {
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if (TE->getOpcode() == Instruction::ExtractElement &&
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!TE->isAltShuffle() &&
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isa<FixedVectorType>(cast<ExtractElementInst>(TE->getMainOp())
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->getVectorOperandType()) &&
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allSameType(TE->Scalars) && allSameBlock(TE->Scalars)) {
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// Check that gather of extractelements can be represented as
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// just a shuffle of a single vector with a single user only.
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OrdersType CurrentOrder;
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bool Reuse =
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canReuseExtract(TE->Scalars, TE->getMainOp(), CurrentOrder);
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if ((Reuse || !CurrentOrder.empty()) &&
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!any_of(VectorizableTree,
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[&TE](const std::unique_ptr<TreeEntry> &Entry) {
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return Entry->State == TreeEntry::NeedToGather &&
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Entry.get() != TE.get() &&
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Entry->isSame(TE->Scalars);
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})) {
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OrderedEntries.insert(TE.get());
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GathersToOrders.try_emplace(TE.get(), CurrentOrder);
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return;
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}
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}
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if (Optional<OrdersType> CurrentOrder =
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findReusedOrderedScalars(*TE.get())) {
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OrderedEntries.insert(TE.get());
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GathersToOrders.try_emplace(TE.get(), CurrentOrder);
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GathersToOrders.try_emplace(TE.get(), *CurrentOrder);
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}
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}
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if (TE->State != TreeEntry::Vectorize)
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NonVectorized.push_back(TE.get());
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});
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// Checks if the operands of the users are reordarable and have only single
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@ -2911,7 +2996,7 @@ void BoUpSLP::reorderBottomToTop(bool IgnoreReorder) {
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for (TreeEntry *TE : OrderedEntries) {
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if (!(TE->State == TreeEntry::Vectorize ||
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(TE->State == TreeEntry::NeedToGather &&
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TE->getOpcode() == Instruction::ExtractElement)) ||
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GathersToOrders.count(TE))) ||
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TE->UserTreeIndices.empty() || !TE->ReuseShuffleIndices.empty() ||
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!all_of(drop_begin(TE->UserTreeIndices),
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[TE](const EdgeInfo &EI) {
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@ -3032,10 +3117,13 @@ void BoUpSLP::reorderBottomToTop(bool IgnoreReorder) {
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}
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// For gathers just need to reorder its scalars.
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for (TreeEntry *Gather : GatherOps) {
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if (!Gather->ReuseShuffleIndices.empty())
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continue;
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assert(Gather->ReorderIndices.empty() &&
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"Unexpected reordering of gathers.");
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if (!Gather->ReuseShuffleIndices.empty()) {
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// Just reorder reuses indices.
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reorderReuses(Gather->ReuseShuffleIndices, Mask);
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continue;
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}
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reorderScalars(Gather->Scalars, Mask);
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OrderedEntries.remove(Gather);
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}
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@ -7369,9 +7457,7 @@ struct SLPVectorizer : public FunctionPass {
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initializeSLPVectorizerPass(*PassRegistry::getPassRegistry());
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}
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bool doInitialization(Module &M) override {
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return false;
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}
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bool doInitialization(Module &M) override { return false; }
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bool runOnFunction(Function &F) override {
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if (skipFunction(F))
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@ -32,21 +32,19 @@ define <2 x i64> @build_vec_v2i64(<2 x i64> %v0, <2 x i64> %v1) {
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define void @store_chain_v2i64(i64* %a, i64* %b, i64* %c) {
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; CHECK-LABEL: @store_chain_v2i64(
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; CHECK-NEXT: [[A_1:%.*]] = getelementptr i64, i64* [[A:%.*]], i64 1
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; CHECK-NEXT: [[B_1:%.*]] = getelementptr i64, i64* [[B:%.*]], i64 1
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; CHECK-NEXT: [[C_1:%.*]] = getelementptr i64, i64* [[C:%.*]], i64 1
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; CHECK-NEXT: [[V0_0:%.*]] = load i64, i64* [[A]], align 8
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; CHECK-NEXT: [[V0_1:%.*]] = load i64, i64* [[A_1]], align 8
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; CHECK-NEXT: [[V1_0:%.*]] = load i64, i64* [[B]], align 8
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; CHECK-NEXT: [[V1_1:%.*]] = load i64, i64* [[B_1]], align 8
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; CHECK-NEXT: [[TMP0_0:%.*]] = add i64 [[V0_0]], [[V1_0]]
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; CHECK-NEXT: [[TMP0_1:%.*]] = add i64 [[V0_1]], [[V1_1]]
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; CHECK-NEXT: [[TMP1_0:%.*]] = sub i64 [[V0_0]], [[V1_0]]
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; CHECK-NEXT: [[TMP1_1:%.*]] = sub i64 [[V0_1]], [[V1_1]]
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; CHECK-NEXT: [[TMP2_0:%.*]] = add i64 [[TMP0_0]], [[TMP0_1]]
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; CHECK-NEXT: [[TMP2_1:%.*]] = add i64 [[TMP1_0]], [[TMP1_1]]
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; CHECK-NEXT: store i64 [[TMP2_0]], i64* [[C]], align 8
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; CHECK-NEXT: store i64 [[TMP2_1]], i64* [[C_1]], align 8
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64* [[A:%.*]] to <2 x i64>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
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; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64* [[B:%.*]] to <2 x i64>*
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; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* [[TMP3]], align 8
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; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP2]], [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = sub <2 x i64> [[TMP2]], [[TMP4]]
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; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> [[TMP6]], <2 x i32> <i32 1, i32 2>
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; CHECK-NEXT: [[TMP8:%.*]] = add <2 x i64> [[TMP2]], [[TMP4]]
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; CHECK-NEXT: [[TMP9:%.*]] = sub <2 x i64> [[TMP2]], [[TMP4]]
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; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i64> [[TMP8]], <2 x i64> [[TMP9]], <2 x i32> <i32 0, i32 3>
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; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i64> [[TMP10]], [[TMP7]]
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; CHECK-NEXT: [[TMP12:%.*]] = bitcast i64* [[C:%.*]] to <2 x i64>*
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; CHECK-NEXT: store <2 x i64> [[TMP11]], <2 x i64>* [[TMP12]], align 8
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; CHECK-NEXT: ret void
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;
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%a.0 = getelementptr i64, i64* %a, i64 0
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@ -32,21 +32,19 @@ define <2 x i64> @build_vec_v2i64(<2 x i64> %v0, <2 x i64> %v1) {
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define void @store_chain_v2i64(i64* %a, i64* %b, i64* %c) {
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; CHECK-LABEL: @store_chain_v2i64(
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; CHECK-NEXT: [[A_1:%.*]] = getelementptr i64, i64* [[A:%.*]], i64 1
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; CHECK-NEXT: [[B_1:%.*]] = getelementptr i64, i64* [[B:%.*]], i64 1
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; CHECK-NEXT: [[C_1:%.*]] = getelementptr i64, i64* [[C:%.*]], i64 1
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; CHECK-NEXT: [[V0_0:%.*]] = load i64, i64* [[A]], align 8
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; CHECK-NEXT: [[V0_1:%.*]] = load i64, i64* [[A_1]], align 8
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; CHECK-NEXT: [[V1_0:%.*]] = load i64, i64* [[B]], align 8
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; CHECK-NEXT: [[V1_1:%.*]] = load i64, i64* [[B_1]], align 8
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; CHECK-NEXT: [[TMP0_0:%.*]] = add i64 [[V0_0]], [[V1_0]]
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; CHECK-NEXT: [[TMP0_1:%.*]] = add i64 [[V0_1]], [[V1_1]]
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; CHECK-NEXT: [[TMP1_0:%.*]] = sub i64 [[V0_0]], [[V1_0]]
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; CHECK-NEXT: [[TMP1_1:%.*]] = sub i64 [[V0_1]], [[V1_1]]
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; CHECK-NEXT: [[TMP2_0:%.*]] = add i64 [[TMP0_0]], [[TMP0_1]]
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; CHECK-NEXT: [[TMP2_1:%.*]] = add i64 [[TMP1_0]], [[TMP1_1]]
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; CHECK-NEXT: store i64 [[TMP2_0]], i64* [[C]], align 8
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; CHECK-NEXT: store i64 [[TMP2_1]], i64* [[C_1]], align 8
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64* [[A:%.*]] to <2 x i64>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
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; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64* [[B:%.*]] to <2 x i64>*
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; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* [[TMP3]], align 8
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; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP2]], [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = sub <2 x i64> [[TMP2]], [[TMP4]]
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; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> [[TMP6]], <2 x i32> <i32 1, i32 2>
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; CHECK-NEXT: [[TMP8:%.*]] = add <2 x i64> [[TMP2]], [[TMP4]]
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; CHECK-NEXT: [[TMP9:%.*]] = sub <2 x i64> [[TMP2]], [[TMP4]]
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; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i64> [[TMP8]], <2 x i64> [[TMP9]], <2 x i32> <i32 0, i32 3>
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; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i64> [[TMP10]], [[TMP7]]
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; CHECK-NEXT: [[TMP12:%.*]] = bitcast i64* [[C:%.*]] to <2 x i64>*
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; CHECK-NEXT: store <2 x i64> [[TMP11]], <2 x i64>* [[TMP12]], align 8
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; CHECK-NEXT: ret void
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;
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%a.0 = getelementptr i64, i64* %a, i64 0
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@ -69,22 +69,23 @@ define i32 @jumbled-load-multiuses(i32* noalias nocapture %in, i32* noalias noca
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; CHECK-NEXT: [[GEP_3:%.*]] = getelementptr inbounds i32, i32* [[IN_ADDR]], i64 2
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[IN_ADDR]] to <4 x i32>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP2]], i32 1
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; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> <i32 2, i32 0, i32 1, i32 3>
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[SHUFFLE]], i32 1
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> poison, i32 [[TMP3]], i32 0
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i32 2
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[SHUFFLE]], i32 2
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[TMP5]], i32 1
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP2]], i32 0
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[SHUFFLE]], i32 0
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; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[TMP7]], i32 2
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; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP2]], i32 3
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; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[SHUFFLE]], i32 3
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; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[TMP9]], i32 3
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; CHECK-NEXT: [[TMP11:%.*]] = mul <4 x i32> [[TMP2]], [[TMP10]]
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; CHECK-NEXT: [[TMP11:%.*]] = mul <4 x i32> [[SHUFFLE]], [[TMP10]]
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; CHECK-NEXT: [[GEP_7:%.*]] = getelementptr inbounds i32, i32* [[OUT:%.*]], i64 0
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; CHECK-NEXT: [[GEP_8:%.*]] = getelementptr inbounds i32, i32* [[OUT]], i64 1
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; CHECK-NEXT: [[GEP_9:%.*]] = getelementptr inbounds i32, i32* [[OUT]], i64 2
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; CHECK-NEXT: [[GEP_10:%.*]] = getelementptr inbounds i32, i32* [[OUT]], i64 3
|
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; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP11]], <4 x i32> poison, <4 x i32> <i32 1, i32 3, i32 2, i32 0>
|
||||
; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <4 x i32> [[TMP11]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
|
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; CHECK-NEXT: [[TMP12:%.*]] = bitcast i32* [[GEP_7]] to <4 x i32>*
|
||||
; CHECK-NEXT: store <4 x i32> [[SHUFFLE]], <4 x i32>* [[TMP12]], align 4
|
||||
; CHECK-NEXT: store <4 x i32> [[SHUFFLE1]], <4 x i32>* [[TMP12]], align 4
|
||||
; CHECK-NEXT: ret i32 undef
|
||||
;
|
||||
%in.addr = getelementptr inbounds i32, i32* %in, i64 0
|
||||
|
|
|
|||
|
|
@ -600,21 +600,18 @@ define void @ChecksExtractScores_different_vectors(double* %storeArray, double*
|
|||
; CHECK-NEXT: [[LOADVEC4:%.*]] = load <2 x double>, <2 x double>* [[VECPTR4:%.*]], align 4
|
||||
; CHECK-NEXT: [[EXTRB0:%.*]] = extractelement <2 x double> [[LOADVEC3]], i32 0
|
||||
; CHECK-NEXT: [[EXTRB1:%.*]] = extractelement <2 x double> [[LOADVEC4]], i32 1
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[EXTRB0]], i32 0
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[EXTRA1]], i32 1
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP2]], i32 1
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[TMP5]], i32 0
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x double> [[TMP6]], double [[TMP7]], i32 1
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = fmul <2 x double> [[TMP4]], [[TMP8]]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x double> poison, double [[EXTRA0]], i32 0
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x double> [[TMP10]], double [[EXTRB1]], i32 1
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = fmul <2 x double> [[TMP11]], [[TMP2]]
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = fadd <2 x double> [[TMP12]], [[TMP9]]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[EXTRA1]], i32 0
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[EXTRB0]], i32 1
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP4]], [[TMP2]]
|
||||
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[EXTRA0]], i32 0
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x double> [[TMP6]], double [[EXTRB1]], i32 1
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = fmul <2 x double> [[TMP7]], [[TMP2]]
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = fadd <2 x double> [[TMP8]], [[SHUFFLE]]
|
||||
; CHECK-NEXT: [[SIDX0:%.*]] = getelementptr inbounds double, double* [[STOREARRAY:%.*]], i64 0
|
||||
; CHECK-NEXT: [[SIDX1:%.*]] = getelementptr inbounds double, double* [[STOREARRAY]], i64 1
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = bitcast double* [[SIDX0]] to <2 x double>*
|
||||
; CHECK-NEXT: store <2 x double> [[TMP13]], <2 x double>* [[TMP14]], align 8
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = bitcast double* [[SIDX0]] to <2 x double>*
|
||||
; CHECK-NEXT: store <2 x double> [[TMP9]], <2 x double>* [[TMP10]], align 8
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
%idx0 = getelementptr inbounds double, double* %array, i64 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue