forked from OSchip/llvm-project
[lldb] [ABI/AArch64] Do not add subregs if some of them are present
Fix a bug introduced while refactoring ABIAArch64::AugmentRegisterInfo() that caused subregisters to be added even if they were already present. Instead, abort immediately if at least one subregister is found (following ABIX86). While at it, add a test for that. Differential Revision: https://reviews.llvm.org/D111881
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6a89fefd13
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lldb
source/Plugins/ABI/AArch64
test/API/functionalities/gdb_remote_client
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@ -111,9 +111,6 @@ void ABIAArch64::AugmentRegisterInfo(
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std::array<llvm::Optional<uint32_t>, 32> x_regs;
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std::array<llvm::Optional<uint32_t>, 32> v_regs;
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std::bitset<32> have_w_regs;
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std::bitset<32> have_s_regs;
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std::bitset<32> have_d_regs;
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for (auto it : llvm::enumerate(regs)) {
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lldb_private::DynamicRegisterInfo::Register &info = it.value();
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@ -133,14 +130,11 @@ void ABIAArch64::AugmentRegisterInfo(
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if (get_reg("x"))
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x_regs[reg_num] = it.index();
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if (get_reg("v"))
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else if (get_reg("v"))
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v_regs[reg_num] = it.index();
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if (get_reg("w"))
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have_w_regs[reg_num] = true;
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if (get_reg("s"))
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have_s_regs[reg_num] = true;
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if (get_reg("d"))
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have_d_regs[reg_num] = true;
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// if we have at least one subregister, abort
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else if (get_reg("w") || get_reg("s") || get_reg("d"))
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return;
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}
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// Create aliases for partial registers: wN for xN, and sN/dN for vN.
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@ -582,3 +582,97 @@ class TestGDBServerTargetXML(GDBRemoteTestBase):
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self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'")
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self.match("register read s31",
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["s31 = 128"])
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@skipIfXmlSupportMissing
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@skipIfRemote
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@skipIfLLVMTargetMissing("AArch64")
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def test_aarch64_no_duplicate_subregs(self):
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"""Test that duplicate subregisters are not added."""
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class MyResponder(MockGDBServerResponder):
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reg_data = (
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"0102030405060708" # x0
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"1112131415161718" # x1
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) + 27 * (
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"2122232425262728" # x2..x28
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) + (
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"3132333435363738" # x29 (fp)
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"4142434445464748" # x30 (lr)
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"5152535455565758" # x31 (sp)
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"6162636465666768" # pc
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"71727374" # cpsr
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)
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def qXferRead(self, obj, annex, offset, length):
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if annex == "target.xml":
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return """<?xml version="1.0"?>
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<target>
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<architecture>aarch64</architecture>
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<feature name="org.gnu.gdb.aarch64.core">
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<reg name="x0" bitsize="64" type="int" regnum="0"/>
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<reg name="x1" bitsize="64" type="int" regnum="1"/>
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<reg name="x2" bitsize="64" type="int" regnum="2"/>
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<reg name="x3" bitsize="64" type="int" regnum="3"/>
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<reg name="x4" bitsize="64" type="int" regnum="4"/>
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<reg name="x5" bitsize="64" type="int" regnum="5"/>
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<reg name="x6" bitsize="64" type="int" regnum="6"/>
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<reg name="x7" bitsize="64" type="int" regnum="7"/>
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<reg name="x8" bitsize="64" type="int" regnum="8"/>
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<reg name="x9" bitsize="64" type="int" regnum="9"/>
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<reg name="x10" bitsize="64" type="int" regnum="10"/>
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<reg name="x11" bitsize="64" type="int" regnum="11"/>
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<reg name="x12" bitsize="64" type="int" regnum="12"/>
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<reg name="x13" bitsize="64" type="int" regnum="13"/>
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<reg name="x14" bitsize="64" type="int" regnum="14"/>
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<reg name="x15" bitsize="64" type="int" regnum="15"/>
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<reg name="x16" bitsize="64" type="int" regnum="16"/>
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<reg name="x17" bitsize="64" type="int" regnum="17"/>
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<reg name="x18" bitsize="64" type="int" regnum="18"/>
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<reg name="x19" bitsize="64" type="int" regnum="19"/>
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<reg name="x20" bitsize="64" type="int" regnum="20"/>
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<reg name="x21" bitsize="64" type="int" regnum="21"/>
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<reg name="x22" bitsize="64" type="int" regnum="22"/>
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<reg name="x23" bitsize="64" type="int" regnum="23"/>
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<reg name="x24" bitsize="64" type="int" regnum="24"/>
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<reg name="x25" bitsize="64" type="int" regnum="25"/>
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<reg name="x26" bitsize="64" type="int" regnum="26"/>
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<reg name="x27" bitsize="64" type="int" regnum="27"/>
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<reg name="x28" bitsize="64" type="int" regnum="28"/>
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<reg name="x29" bitsize="64" type="int" regnum="29"/>
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<reg name="x30" bitsize="64" type="int" regnum="30"/>
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<reg name="sp" bitsize="64" type="data_ptr" regnum="31"/>
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<reg name="pc" bitsize="64" type="code_ptr" regnum="32"/>
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<reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/>
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<reg name="w0" bitsize="32" type="int" regnum="34" value_regnums="0"/>
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</feature>
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</target>""", False
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else:
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return None, False
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def readRegister(self, regnum):
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return ""
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def readRegisters(self):
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return self.reg_data
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def haltReason(self):
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return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"
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self.server.responder = MyResponder()
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target = self.createTarget("basic_eh_frame-aarch64.yaml")
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process = self.connect(target)
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lldbutil.expect_state_changes(self, self.dbg.GetListener(), process,
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[lldb.eStateStopped])
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self.match("register read x0",
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["x0 = 0x0807060504030201"])
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# w0 comes from target.xml
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self.match("register read w0",
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["w0 = 0x04030201"])
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self.match("register read x1",
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["x1 = 0x1817161514131211"])
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# w1 should not be added
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self.match("register read w1",
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["error: Invalid register name 'w1'."],
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error=True)
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