forked from OSchip/llvm-project
AArch64: Fix end iterator dereference
Not all blocks have terminators. I'm not sure how this wasn't crashing before. llvm-svn: 277427
This commit is contained in:
Matt Arsenault
parent
f5cadce1cd
commit
f7065e15f8
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@ -84,12 +84,12 @@ class AArch64BranchRelaxation : public MachineFunctionPass {
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bool relaxBranchInstructions();
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void scanFunction();
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MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
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MachineBasicBlock *splitBlockBeforeInstr(MachineInstr &MI);
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void adjustBlockOffsets(MachineBasicBlock &MBB);
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bool isBlockInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
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bool fixupConditionalBranch(MachineInstr *MI);
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bool isBlockInRange(MachineInstr &MI, MachineBasicBlock &BB, unsigned Disp);
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bool fixupConditionalBranch(MachineInstr &MI);
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void computeBlockSize(const MachineBasicBlock &MBB);
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unsigned getInstrOffset(MachineInstr *MI) const;
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unsigned getInstrOffset(MachineInstr &MI) const;
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void dumpBBs();
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void verify();
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@ -180,8 +180,8 @@ void AArch64BranchRelaxation::computeBlockSize(const MachineBasicBlock &MBB) {
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/// getInstrOffset - Return the current offset of the specified machine
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/// instruction from the start of the function. This offset changes as stuff is
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/// moved around inside the function.
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unsigned AArch64BranchRelaxation::getInstrOffset(MachineInstr *MI) const {
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MachineBasicBlock *MBB = MI->getParent();
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unsigned AArch64BranchRelaxation::getInstrOffset(MachineInstr &MI) const {
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MachineBasicBlock *MBB = MI.getParent();
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// The offset is composed of two things: the sum of the sizes of all MBB's
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// before this instruction's block, and the offset from the start of the block
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@ -189,10 +189,11 @@ unsigned AArch64BranchRelaxation::getInstrOffset(MachineInstr *MI) const {
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unsigned Offset = BlockInfo[MBB->getNumber()].Offset;
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// Sum instructions before MI in MBB.
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for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
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for (MachineBasicBlock::iterator I = MBB->begin(); &*I != &MI; ++I) {
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assert(I != MBB->end() && "Didn't find MI in its own basic block?");
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Offset += TII->getInstSizeInBytes(*I);
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}
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return Offset;
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}
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@ -217,8 +218,8 @@ void AArch64BranchRelaxation::adjustBlockOffsets(MachineBasicBlock &Start) {
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/// and must be updated by the caller! Other transforms follow using this
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/// utility function, so no point updating now rather than waiting.
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MachineBasicBlock *
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AArch64BranchRelaxation::splitBlockBeforeInstr(MachineInstr *MI) {
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MachineBasicBlock *OrigBB = MI->getParent();
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AArch64BranchRelaxation::splitBlockBeforeInstr(MachineInstr &MI) {
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MachineBasicBlock *OrigBB = MI.getParent();
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// Create a new MBB for the code after the OrigBB.
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MachineBasicBlock *NewBB =
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@ -226,7 +227,7 @@ AArch64BranchRelaxation::splitBlockBeforeInstr(MachineInstr *MI) {
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MF->insert(++OrigBB->getIterator(), NewBB);
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// Splice the instructions starting with MI over to NewBB.
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NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
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NewBB->splice(NewBB->end(), OrigBB, MI.getIterator(), OrigBB->end());
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// Add an unconditional branch from OrigBB to NewBB.
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// Note the new unconditional branch is not being recorded.
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@ -258,18 +259,18 @@ AArch64BranchRelaxation::splitBlockBeforeInstr(MachineInstr *MI) {
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/// isBlockInRange - Returns true if the distance between specific MI and
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/// specific BB can fit in MI's displacement field.
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bool AArch64BranchRelaxation::isBlockInRange(MachineInstr *MI,
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MachineBasicBlock *DestBB,
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bool AArch64BranchRelaxation::isBlockInRange(MachineInstr &MI,
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MachineBasicBlock &DestBB,
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unsigned Bits) {
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unsigned MaxOffs = ((1 << (Bits - 1)) - 1) << 2;
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unsigned BrOffset = getInstrOffset(MI);
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unsigned DestOffset = BlockInfo[DestBB->getNumber()].Offset;
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unsigned DestOffset = BlockInfo[DestBB.getNumber()].Offset;
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DEBUG(dbgs() << "Branch of destination BB#" << DestBB->getNumber()
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<< " from BB#" << MI->getParent()->getNumber()
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<< " max delta=" << MaxOffs << " from " << getInstrOffset(MI)
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DEBUG(dbgs() << "Branch of destination BB#" << DestBB.getNumber()
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<< " from BB#" << MI.getParent()->getNumber()
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<< " max delta=" << MaxOffs << " from " << BrOffset
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<< " to " << DestOffset << " offset "
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<< int(DestOffset - BrOffset) << "\t" << *MI);
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<< static_cast<int>(DestOffset - BrOffset) << '\t' << MI);
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// Branch before the Dest.
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if (BrOffset <= DestOffset)
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@ -294,21 +295,21 @@ static bool isConditionalBranch(unsigned Opc) {
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}
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}
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static MachineBasicBlock *getDestBlock(MachineInstr *MI) {
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switch (MI->getOpcode()) {
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static MachineBasicBlock *getDestBlock(MachineInstr &MI) {
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switch (MI.getOpcode()) {
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default:
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llvm_unreachable("unexpected opcode!");
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case AArch64::TBZW:
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case AArch64::TBNZW:
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case AArch64::TBZX:
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case AArch64::TBNZX:
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return MI->getOperand(2).getMBB();
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return MI.getOperand(2).getMBB();
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case AArch64::CBZW:
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case AArch64::CBNZW:
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case AArch64::CBZX:
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case AArch64::CBNZX:
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case AArch64::Bcc:
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return MI->getOperand(1).getMBB();
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return MI.getOperand(1).getMBB();
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}
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}
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@ -347,17 +348,17 @@ static unsigned getBranchDisplacementBits(unsigned Opc) {
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}
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}
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static inline void invertBccCondition(MachineInstr *MI) {
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assert(MI->getOpcode() == AArch64::Bcc && "Unexpected opcode!");
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AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(0).getImm();
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static inline void invertBccCondition(MachineInstr &MI) {
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assert(MI.getOpcode() == AArch64::Bcc && "Unexpected opcode!");
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AArch64CC::CondCode CC = (AArch64CC::CondCode)MI.getOperand(0).getImm();
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CC = AArch64CC::getInvertedCondCode(CC);
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MI->getOperand(0).setImm((int64_t)CC);
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MI.getOperand(0).setImm((int64_t)CC);
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}
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/// fixupConditionalBranch - Fix up a conditional branch whose destination is
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/// too far away to fit in its displacement field. It is converted to an inverse
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/// conditional branch + an unconditional branch to the destination.
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bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr *MI) {
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bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
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MachineBasicBlock *DestBB = getDestBlock(MI);
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// Add an unconditional branch to the destination and invert the branch
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@ -371,11 +372,11 @@ bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr *MI) {
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// If the branch is at the end of its MBB and that has a fall-through block,
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// direct the updated conditional branch to the fall-through block. Otherwise,
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// split the MBB before the next instruction.
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MachineBasicBlock *MBB = MI->getParent();
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MachineBasicBlock *MBB = MI.getParent();
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MachineInstr *BMI = &MBB->back();
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bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
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bool NeedSplit = (BMI != &MI) || !BBHasFallthrough(MBB);
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if (BMI != MI) {
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if (BMI != &MI) {
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if (std::next(MachineBasicBlock::iterator(MI)) ==
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std::prev(MBB->getLastNonDebugInstr()) &&
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BMI->getOpcode() == AArch64::B) {
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@ -387,20 +388,20 @@ bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr *MI) {
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// bne L2
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// b L1
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MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
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if (isBlockInRange(MI, NewDest,
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getBranchDisplacementBits(MI->getOpcode()))) {
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if (isBlockInRange(MI, *NewDest,
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getBranchDisplacementBits(MI.getOpcode()))) {
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DEBUG(dbgs() << " Invert condition and swap its destination with "
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<< *BMI);
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BMI->getOperand(0).setMBB(DestBB);
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unsigned OpNum = (MI->getOpcode() == AArch64::TBZW ||
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MI->getOpcode() == AArch64::TBNZW ||
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MI->getOpcode() == AArch64::TBZX ||
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MI->getOpcode() == AArch64::TBNZX)
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unsigned OpNum = (MI.getOpcode() == AArch64::TBZW ||
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MI.getOpcode() == AArch64::TBNZW ||
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MI.getOpcode() == AArch64::TBZX ||
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MI.getOpcode() == AArch64::TBNZX)
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? 2
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: 1;
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MI->getOperand(OpNum).setMBB(NewDest);
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MI->setDesc(TII->get(getOppositeConditionOpcode(MI->getOpcode())));
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if (MI->getOpcode() == AArch64::Bcc)
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MI.getOperand(OpNum).setMBB(NewDest);
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MI.setDesc(TII->get(getOppositeConditionOpcode(MI.getOpcode())));
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if (MI.getOpcode() == AArch64::Bcc)
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invertBccCondition(MI);
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return true;
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}
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@ -432,23 +433,24 @@ bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr *MI) {
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<< ", invert condition and change dest. to BB#"
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<< NextBB->getNumber() << "\n");
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unsigned OppositeCondOpc = getOppositeConditionOpcode(MI.getOpcode());
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// Insert a new conditional branch and a new unconditional branch.
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MachineInstrBuilder MIB = BuildMI(
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MBB, DebugLoc(), TII->get(getOppositeConditionOpcode(MI->getOpcode())))
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.addOperand(MI->getOperand(0));
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if (MI->getOpcode() == AArch64::TBZW || MI->getOpcode() == AArch64::TBNZW ||
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MI->getOpcode() == AArch64::TBZX || MI->getOpcode() == AArch64::TBNZX)
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MIB.addOperand(MI->getOperand(1));
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if (MI->getOpcode() == AArch64::Bcc)
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invertBccCondition(MIB);
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MachineInstrBuilder MIB = BuildMI(MBB, DebugLoc(), TII->get(OppositeCondOpc))
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.addOperand(MI.getOperand(0));
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if (MI.getOpcode() == AArch64::TBZW || MI.getOpcode() == AArch64::TBNZW ||
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MI.getOpcode() == AArch64::TBZX || MI.getOpcode() == AArch64::TBNZX)
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MIB.addOperand(MI.getOperand(1));
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if (MI.getOpcode() == AArch64::Bcc)
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invertBccCondition(*MIB);
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MIB.addMBB(NextBB);
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BlockInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
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BuildMI(MBB, DebugLoc(), TII->get(AArch64::B)).addMBB(DestBB);
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BlockInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
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// Remove the old conditional branch. It may or may not still be in MBB.
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BlockInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
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MI->eraseFromParent();
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BlockInfo[MI.getParent()->getNumber()].Size -= TII->getInstSizeInBytes(MI);
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MI.eraseFromParent();
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// Finally, keep the block offsets up to date.
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adjustBlockOffsets(*MBB);
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@ -461,11 +463,15 @@ bool AArch64BranchRelaxation::relaxBranchInstructions() {
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// end() for termination.
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for (MachineFunction::iterator I = MF->begin(); I != MF->end(); ++I) {
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MachineBasicBlock &MBB = *I;
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MachineInstr &MI = *MBB.getFirstTerminator();
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MachineBasicBlock::iterator J = MBB.getFirstTerminator();
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if (J == MBB.end())
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continue;
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MachineInstr &MI = *J;
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if (isConditionalBranch(MI.getOpcode()) &&
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!isBlockInRange(&MI, getDestBlock(&MI),
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!isBlockInRange(MI, *getDestBlock(MI),
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getBranchDisplacementBits(MI.getOpcode()))) {
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fixupConditionalBranch(&MI);
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fixupConditionalBranch(MI);
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++NumRelaxed;
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Changed = true;
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}
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