forked from OSchip/llvm-project
[RISCV] Add zext.h/zext.w to RISCVTTIImpl::getIntImmCostInst.
If we have these instructions, we don't need to hoist the immediate for an AND that would match them. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D107783
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@ -52,8 +52,15 @@ InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
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// split up large offsets in GEP into better parts than ConstantHoisting
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// can.
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return TTI::TCC_Free;
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case Instruction::Add:
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case Instruction::And:
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// zext.h
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if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
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return TTI::TCC_Free;
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// zext.w
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if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZbb())
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return TTI::TCC_Free;
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LLVM_FALLTHROUGH;
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case Instruction::Add:
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case Instruction::Or:
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case Instruction::Xor:
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case Instruction::Mul:
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@ -36,3 +36,39 @@ define i128 @test4(i128 %a) nounwind {
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%2 = add i128 %1, 12297829382473034410122878
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ret i128 %2
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}
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; Check that we hoist zext.h without Zbb.
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define i32 @test5(i32 %a) nounwind {
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; CHECK-LABEL: test5
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; CHECK: %const = bitcast i32 65535 to i32
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%1 = and i32 %a, 65535
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%2 = and i32 %1, 65535
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ret i32 %2
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}
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; Check that we don't hoist zext.h with 65535 with Zbb.
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define i32 @test6(i32 %a) nounwind "target-features"="+experimental-zbb" {
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; CHECK-LABEL: test6
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; CHECK: and i32 %a, 65535
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%1 = and i32 %a, 65535
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%2 = and i32 %1, 65535
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ret i32 %2
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}
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; Check that we hoist zext.w without Zba.
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define i64 @test7(i64 %a) nounwind {
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; CHECK-LABEL: test7
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; CHECK: %const = bitcast i64 4294967295 to i64
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%1 = and i64 %a, 4294967295
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%2 = and i64 %1, 4294967295
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ret i64 %2
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}
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; Check that we don't hoist zext.w with Zba.
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define i64 @test8(i64 %a) nounwind "target-features"="+experimental-zbb" {
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; CHECK-LABEL: test8
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; CHECK: and i64 %a, 4294967295
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%1 = and i64 %a, 4294967295
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%2 = and i64 %1, 4294967295
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ret i64 %2
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}
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