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[InstCombine] Add tests for fshl/fshr with masked operands; NFC 

Baseline tests for D60660.

Patch by Shawn Landden.

Differential Revision: https://reviews.llvm.org/D60688

llvm-svn: 358514
This commit is contained in:
Nikita Popov 2019-04-16 19:05:40 +00:00
parent f136c46bd6
commit f700081a7d
1 changed files with 81 additions and 0 deletions
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81
llvm/test/Transforms/InstCombine/fsh.ll
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@ -559,3 +559,84 @@ define i16 @fshr_bswap(i16 %x) {
ret i16 %r
}
define i32 @fshl_mask_args_same1(i32 %a) {
; CHECK-LABEL: @fshl_mask_args_same1(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -65536
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 16)
; CHECK-NEXT: ret i32 [[TMP2]]
;
%tmp1 = and i32 %a, 4294901760 ; 0xffff0000
%tmp2 = call i32 @llvm.fshl.i32(i32 %tmp1, i32 %tmp1, i32 16)
ret i32 %tmp2
}
define i32 @fshl_mask_args_same2(i32 %a) {
; CHECK-LABEL: @fshl_mask_args_same2(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 255
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 8)
; CHECK-NEXT: ret i32 [[TMP2]]
;
%tmp1 = and i32 %a, 255
%tmp2 = call i32 @llvm.fshl.i32(i32 %tmp1, i32 %tmp1, i32 8)
ret i32 %tmp2
}
define i32 @fshl_mask_args_same3(i32 %a) {
; CHECK-LABEL: @fshl_mask_args_same3(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 255
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 24)
; CHECK-NEXT: ret i32 [[TMP2]]
;
%tmp1 = and i32 %a, 255
%tmp2 = call i32 @llvm.fshl.i32(i32 %tmp1, i32 %tmp1, i32 24)
ret i32 %tmp2
}
define i32 @fshl_mask_args_different(i32 %a) {
; CHECK-LABEL: @fshl_mask_args_different(
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[A:%.*]], -65536
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A]], -16777216
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP2]], i32 [[TMP1]], i32 17)
; CHECK-NEXT: ret i32 [[TMP3]]
;
%tmp2 = and i32 %a, 4294901760 ; 0xfffff00f
%tmp1 = and i32 %a, 4278190080 ; 0xff00f00f
%tmp3 = call i32 @llvm.fshl.i32(i32 %tmp2, i32 %tmp1, i32 17)
ret i32 %tmp3
}
define <2 x i31> @fshr_mask_args_same_vector(<2 x i31> %a) {
; CHECK-LABEL: @fshr_mask_args_same_vector(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i31> [[A:%.*]], <i31 1000, i31 1000>
; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> [[A]], <2 x i31> [[TMP1]], <2 x i31> <i31 10, i31 10>)
; CHECK-NEXT: ret <2 x i31> [[TMP3]]
;
%tmp1 = and <2 x i31> %a, <i31 1000, i31 1000>
%tmp2 = and <2 x i31> %a, <i31 6442450943, i31 6442450943>
%tmp3 = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> %tmp2, <2 x i31> %tmp1, <2 x i31> <i31 10, i31 10>)
ret <2 x i31> %tmp3
}
define <2 x i32> @fshr_mask_args_same_vector2(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: @fshr_mask_args_same_vector2(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[A:%.*]], <i32 1000000, i32 100000>
; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 29, i32 29>)
; CHECK-NEXT: ret <2 x i32> [[TMP3]]
;
%tmp1 = and <2 x i32> %a, <i32 1000000, i32 100000>
%tmp2 = and <2 x i32> %a, <i32 6442450943, i32 6442450943>
%tmp3 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> <i32 3, i32 3>)
ret <2 x i32> %tmp3
}
define <2 x i31> @fshr_mask_args_same_vector3_different_but_still_prunable(<2 x i31> %a) {
; CHECK-LABEL: @fshr_mask_args_same_vector3_different_but_still_prunable(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i31> [[A:%.*]], <i31 1000, i31 1000>
; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> [[A]], <2 x i31> [[TMP1]], <2 x i31> <i31 10, i31 3>)
; CHECK-NEXT: ret <2 x i31> [[TMP3]]
;
%tmp1 = and <2 x i31> %a, <i31 1000, i31 1000>
%tmp2 = and <2 x i31> %a, <i31 6442450943, i31 6442450943>
%tmp3 = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> %tmp2, <2 x i31> %tmp1, <2 x i31> <i31 10, i31 3>)
ret <2 x i31> %tmp3
}