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[TwoAddressInstructionPass] Improve tryInstructionCommute of X86 FMA and vpternlog instructions 

These instructions have 3 operands that can be commuted. The first commute we find may not be the best. So we should keep searching if we performed an aggressive commute. There may still be an operand that is killed or a physical register constraint that might be better.

Differential Revision: https://reviews.llvm.org/D44324

llvm-svn: 327188
This commit is contained in:
Craig Topper 2018-03-09 23:36:58 +00:00
parent c332ae8be8
commit f6ff51fc62
2 changed files with 16 additions and 9 deletions
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19
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -1205,6 +1205,7 @@ bool TwoAddressInstructionPass::tryInstructionCommute(MachineInstr *MI,
if (!MI->isCommutable())
return false;
bool MadeChange = false;
unsigned DstOpReg = MI->getOperand(DstOpIdx).getReg();
unsigned BaseOpReg = MI->getOperand(BaseOpIdx).getReg();
unsigned OpsNum = MI->getDesc().getNumOperands();
@ -1223,8 +1224,8 @@ bool TwoAddressInstructionPass::tryInstructionCommute(MachineInstr *MI,
// If OtherOp dies but BaseOp does not, swap the OtherOp and BaseOp
// operands. This makes the live ranges of DstOp and OtherOp joinable.
bool DoCommute =
!BaseOpKilled && isKilled(*MI, OtherOpReg, MRI, TII, LIS, false);
bool OtherOpKilled = isKilled(*MI, OtherOpReg, MRI, TII, LIS, false);
bool DoCommute = !BaseOpKilled && OtherOpKilled;
if (!DoCommute &&
isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg, MI, Dist)) {
@ -1235,13 +1236,21 @@ bool TwoAddressInstructionPass::tryInstructionCommute(MachineInstr *MI,
// If it's profitable to commute, try to do so.
if (DoCommute && commuteInstruction(MI, DstOpIdx, BaseOpIdx, OtherOpIdx,
Dist)) {
MadeChange = true;
++NumCommuted;
if (AggressiveCommute)
if (AggressiveCommute) {
++NumAggrCommuted;
return true;
// There might be more than two commutable operands, update BaseOp and
// continue scanning.
BaseOpReg = OtherOpReg;
BaseOpKilled = OtherOpKilled;
continue;
}
// If this was a commute based on kill, we won't do better continuing.
return MadeChange;
}
}
return false;
return MadeChange;
}
/// For the case where an instruction has a single pair of tied register

6
llvm/test/CodeGen/X86/avx512-vpternlog-commute.ll
View File

@ -27,8 +27,7 @@ define <16 x i32> @vpternlog_v16i32_102(<16 x i32> %x0, <16 x i32> %x1, <16 x i3
define <16 x i32> @vpternlog_v16i32_210(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2) {
; CHECK-LABEL: vpternlog_v16i32_210:
; CHECK: ## %bb.0:
; CHECK-NEXT: vpternlogd $78, %zmm0, %zmm2, %zmm1
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: vpternlogd $92, %zmm1, %zmm2, %zmm0
; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.mask.pternlog.d.512(<16 x i32> %x2, <16 x i32> %x1, <16 x i32> %x0, i32 114, i16 -1)
ret <16 x i32> %res
@ -434,8 +433,7 @@ define <16 x i32> @vpternlog_v16i32_210_maskz(<16 x i32> %x0, <16 x i32> %x1, <1
; CHECK-LABEL: vpternlog_v16i32_210_maskz:
; CHECK: ## %bb.0:
; CHECK-NEXT: kmovd %edi, %k1
; CHECK-NEXT: vpternlogd $78, %zmm0, %zmm2, %zmm1 {%k1} {z}
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: vpternlogd $92, %zmm1, %zmm2, %zmm0 {%k1} {z}
; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.maskz.pternlog.d.512(<16 x i32> %x2, <16 x i32> %x1, <16 x i32> %x0, i32 114, i16 %mask)
ret <16 x i32> %res