forked from OSchip/llvm-project
[InstCombine][X86] Add MULDQ/MULUDQ constant folding support
llvm-svn: 292793
This commit is contained in:
Simon Pilgrim
parent
2fec7e4f44
commit
f6f3a36159
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@ -510,16 +510,53 @@ static Value *simplifyX86varShift(const IntrinsicInst &II,
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return Builder.CreateAShr(Vec, ShiftVec);
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}
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static Value *simplifyX86muldq(const IntrinsicInst &II) {
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static Value *simplifyX86muldq(const IntrinsicInst &II,
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InstCombiner::BuilderTy &Builder) {
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Value *Arg0 = II.getArgOperand(0);
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Value *Arg1 = II.getArgOperand(1);
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Type *ResTy = II.getType();
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assert(Arg0->getType()->getScalarSizeInBits() == 32 &&
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Arg1->getType()->getScalarSizeInBits() == 32 &&
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ResTy->getScalarSizeInBits() == 64 && "Unexpected muldq/muludq types");
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// muldq/muludq(undef, undef) -> zero (matches generic mul behavior)
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if (isa<UndefValue>(Arg0) && isa<UndefValue>(Arg1))
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return ConstantAggregateZero::get(ResTy);
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return nullptr;
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// Constant folding.
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// PMULDQ = (mul(vXi64 sext(shuffle<0,2,..>(Arg0)),
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// vXi64 sext(shuffle<0,2,..>(Arg1))))
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// PMULUDQ = (mul(vXi64 zext(shuffle<0,2,..>(Arg0)),
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// vXi64 zext(shuffle<0,2,..>(Arg1))))
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if (!isa<Constant>(Arg0) || !isa<Constant>(Arg1))
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return nullptr;
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unsigned NumElts = ResTy->getVectorNumElements();
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assert(Arg0->getType()->getVectorNumElements() == (2 * NumElts) &&
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Arg1->getType()->getVectorNumElements() == (2 * NumElts) &&
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"Unexpected muldq/muludq types");
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unsigned IntrinsicID = II.getIntrinsicID();
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bool IsSigned = (Intrinsic::x86_sse41_pmuldq == IntrinsicID ||
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Intrinsic::x86_avx2_pmul_dq == IntrinsicID ||
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Intrinsic::x86_avx512_pmul_dq_512 == IntrinsicID);
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SmallVector<unsigned, 16> ShuffleMask;
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for (unsigned i = 0; i != NumElts; ++i)
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ShuffleMask.push_back(i * 2);
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auto *LHS = Builder.CreateShuffleVector(Arg0, Arg0, ShuffleMask);
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auto *RHS = Builder.CreateShuffleVector(Arg1, Arg1, ShuffleMask);
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if (IsSigned) {
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LHS = Builder.CreateSExt(LHS, ResTy);
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RHS = Builder.CreateSExt(RHS, ResTy);
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} else {
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LHS = Builder.CreateZExt(LHS, ResTy);
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RHS = Builder.CreateZExt(RHS, ResTy);
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}
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return Builder.CreateMul(LHS, RHS);
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}
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static Value *simplifyX86movmsk(const IntrinsicInst &II,
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@ -2154,7 +2191,7 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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case Intrinsic::x86_avx2_pmulu_dq:
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case Intrinsic::x86_avx512_pmul_dq_512:
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case Intrinsic::x86_avx512_pmulu_dq_512: {
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if (Value *V = simplifyX86muldq(*II))
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if (Value *V = simplifyX86muldq(*II, *Builder))
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return replaceInstUsesWith(*II, V);
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unsigned VWidth = II->getType()->getVectorNumElements();
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@ -55,8 +55,7 @@ define <8 x i64> @undef_pmuldq_512(<16 x i32> %a0, <16 x i32> %a1) {
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define <2 x i64> @undef_zero_pmuludq_128(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK-LABEL: @undef_zero_pmuludq_128(
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; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 undef>)
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; CHECK-NEXT: ret <2 x i64> [[TMP1]]
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; CHECK-NEXT: ret <2 x i64> zeroinitializer
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;
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%1 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> undef, <4 x i32> zeroinitializer)
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ret <2 x i64> %1
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@ -64,8 +63,7 @@ define <2 x i64> @undef_zero_pmuludq_128(<4 x i32> %a0, <4 x i32> %a1) {
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define <4 x i64> @undef_zero_pmuludq_256(<8 x i32> %a0, <8 x i32> %a1) {
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; CHECK-LABEL: @undef_zero_pmuludq_256(
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; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> <i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef>, <8 x i32> undef)
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; CHECK-NEXT: ret <4 x i64> [[TMP1]]
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; CHECK-NEXT: ret <4 x i64> zeroinitializer
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;
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%1 = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> zeroinitializer, <8 x i32> undef)
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ret <4 x i64> %1
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@ -73,8 +71,7 @@ define <4 x i64> @undef_zero_pmuludq_256(<8 x i32> %a0, <8 x i32> %a1) {
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define <8 x i64> @undef_zero_pmuludq_512(<16 x i32> %a0, <16 x i32> %a1) {
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; CHECK-LABEL: @undef_zero_pmuludq_512(
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; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> undef, <16 x i32> <i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef>)
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; CHECK-NEXT: ret <8 x i64> [[TMP1]]
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; CHECK-NEXT: ret <8 x i64> zeroinitializer
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;
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%1 = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> undef, <16 x i32> zeroinitializer)
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ret <8 x i64> %1
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@ -82,8 +79,7 @@ define <8 x i64> @undef_zero_pmuludq_512(<16 x i32> %a0, <16 x i32> %a1) {
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define <2 x i64> @undef_zero_pmuldq_128(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK-LABEL: @undef_zero_pmuldq_128(
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; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> <i32 0, i32 undef, i32 0, i32 undef>, <4 x i32> undef)
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; CHECK-NEXT: ret <2 x i64> [[TMP1]]
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; CHECK-NEXT: ret <2 x i64> zeroinitializer
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;
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%1 = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> zeroinitializer, <4 x i32> undef)
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ret <2 x i64> %1
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@ -91,8 +87,7 @@ define <2 x i64> @undef_zero_pmuldq_128(<4 x i32> %a0, <4 x i32> %a1) {
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define <4 x i64> @undef_zero_pmuldq_256(<8 x i32> %a0, <8 x i32> %a1) {
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; CHECK-LABEL: @undef_zero_pmuldq_256(
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; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32> undef, <8 x i32> <i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef>)
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; CHECK-NEXT: ret <4 x i64> [[TMP1]]
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; CHECK-NEXT: ret <4 x i64> zeroinitializer
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;
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%1 = call <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32> undef, <8 x i32> zeroinitializer)
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ret <4 x i64> %1
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@ -100,8 +95,7 @@ define <4 x i64> @undef_zero_pmuldq_256(<8 x i32> %a0, <8 x i32> %a1) {
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define <8 x i64> @undef_zero_pmuldq_512(<16 x i32> %a0, <16 x i32> %a1) {
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; CHECK-LABEL: @undef_zero_pmuldq_512(
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; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> <i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef>, <16 x i32> undef)
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; CHECK-NEXT: ret <8 x i64> [[TMP1]]
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; CHECK-NEXT: ret <8 x i64> zeroinitializer
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;
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%1 = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> zeroinitializer, <16 x i32> undef)
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ret <8 x i64> %1
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@ -113,8 +107,7 @@ define <8 x i64> @undef_zero_pmuldq_512(<16 x i32> %a0, <16 x i32> %a1) {
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define <2 x i64> @fold_pmuludq_128(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK-LABEL: @fold_pmuludq_128(
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; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> <i32 -1, i32 undef, i32 -1, i32 undef>, <4 x i32> <i32 2147483647, i32 undef, i32 1, i32 undef>)
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; CHECK-NEXT: ret <2 x i64> [[TMP1]]
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; CHECK-NEXT: ret <2 x i64> <i64 9223372030412324865, i64 4294967295>
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;
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%1 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 2147483647, i32 1, i32 1, i32 3>)
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ret <2 x i64> %1
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@ -122,8 +115,7 @@ define <2 x i64> @fold_pmuludq_128(<4 x i32> %a0, <4 x i32> %a1) {
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define <4 x i64> @fold_pmuludq_256(<8 x i32> %a0, <8 x i32> %a1) {
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; CHECK-LABEL: @fold_pmuludq_256(
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; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> <i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef>, <8 x i32> <i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef>)
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; CHECK-NEXT: ret <4 x i64> [[TMP1]]
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; CHECK-NEXT: ret <4 x i64> zeroinitializer
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;
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%1 = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> zeroinitializer, <8 x i32> zeroinitializer)
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ret <4 x i64> %1
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@ -131,8 +123,7 @@ define <4 x i64> @fold_pmuludq_256(<8 x i32> %a0, <8 x i32> %a1) {
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define <8 x i64> @fold_pmuludq_512(<16 x i32> %a0, <16 x i32> %a1) {
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; CHECK-LABEL: @fold_pmuludq_512(
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; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 undef, i32 undef, i32 -1, i32 undef, i32 65536, i32 undef, i32 -65536, i32 undef>, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 255, i32 undef, i32 65535, i32 undef, i32 0, i32 undef, i32 -65535, i32 undef, i32 2147483647, i32 undef, i32 65536, i32 undef>)
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; CHECK-NEXT: ret <8 x i64> [[TMP1]]
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; CHECK-NEXT: ret <8 x i64> <i64 0, i64 0, i64 255, i64 131070, i64 0, i64 -281474976645121, i64 140737488289792, i64 281470681743360>
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;
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%1 = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> <i32 0, i32 0, i32 undef, i32 0, i32 1, i32 1, i32 2, i32 2, i32 undef, i32 undef, i32 -1, i32 -1, i32 65536, i32 -1, i32 -65536, i32 undef>, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 1, i32 255, i32 -256, i32 65535, i32 -65536, i32 0, i32 -1, i32 -65535, i32 -65535, i32 2147483647, i32 2147483648, i32 65536, i32 -65535>)
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ret <8 x i64> %1
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@ -140,8 +131,7 @@ define <8 x i64> @fold_pmuludq_512(<16 x i32> %a0, <16 x i32> %a1) {
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define <2 x i64> @fold_pmuldq_128(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK-LABEL: @fold_pmuldq_128(
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; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> <i32 undef, i32 undef, i32 -1, i32 undef>, <4 x i32> <i32 undef, i32 undef, i32 -2, i32 undef>)
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; CHECK-NEXT: ret <2 x i64> [[TMP1]]
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; CHECK-NEXT: ret <2 x i64> <i64 0, i64 2>
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;
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%1 = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> <i32 undef, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 undef, i32 1, i32 -2, i32 3>)
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ret <2 x i64> %1
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@ -149,8 +139,7 @@ define <2 x i64> @fold_pmuldq_128(<4 x i32> %a0, <4 x i32> %a1) {
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define <4 x i64> @fold_pmuldq_256(<8 x i32> %a0, <8 x i32> %a1) {
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; CHECK-LABEL: @fold_pmuldq_256(
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; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32> <i32 undef, i32 undef, i32 -65535, i32 undef, i32 65536, i32 undef, i32 -2147483648, i32 undef>, <8 x i32> <i32 0, i32 undef, i32 -65535, i32 undef, i32 2147483647, i32 undef, i32 65536, i32 undef>)
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; CHECK-NEXT: ret <4 x i64> [[TMP1]]
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; CHECK-NEXT: ret <4 x i64> <i64 0, i64 4294836225, i64 140737488289792, i64 -140737488355328>
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;
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%1 = call <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32> <i32 undef, i32 1, i32 -65535, i32 128, i32 65536, i32 2147483647, i32 -2147483648, i32 65536>, <8 x i32> <i32 0, i32 -1, i32 -65535, i32 -65535, i32 2147483647, i32 2147483648, i32 65536, i32 -65535>)
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ret <4 x i64> %1
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@ -158,8 +147,7 @@ define <4 x i64> @fold_pmuldq_256(<8 x i32> %a0, <8 x i32> %a1) {
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define <8 x i64> @fold_pmuldq_512(<16 x i32> %a0, <16 x i32> %a1) {
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; CHECK-LABEL: @fold_pmuldq_512(
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; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> <i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef>, <16 x i32> <i32 undef, i32 undef, i32 -3, i32 undef, i32 8, i32 undef, i32 -256, i32 undef, i32 undef, i32 undef, i32 -65535, i32 undef, i32 65536, i32 undef, i32 -2147483648, i32 undef>)
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; CHECK-NEXT: ret <8 x i64> [[TMP1]]
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; CHECK-NEXT: ret <8 x i64> zeroinitializer
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;
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%1 = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> zeroinitializer, <16 x i32> <i32 undef, i32 -1, i32 -3, i32 -1, i32 8, i32 10, i32 -256, i32 65536, i32 undef, i32 1, i32 -65535, i32 128, i32 65536, i32 2147483647, i32 -2147483648, i32 65536>)
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ret <8 x i64> %1
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