From f6df30852b59e828b2f6b0a0f3422110d6ca8a58 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Tue, 9 Jun 2009 19:30:45 +0000 Subject: [PATCH] Add the beginnings of an implementatation of lazy liveness analysis, based on "Fast Liveness Checking for SSA-form Programs" by Boissinot, et al. This is still very early, hasn't been tested, and is not yet well documented. More to come soon. llvm-svn: 73141 --- llvm/include/llvm/CodeGen/LazyLiveness.h | 62 +++++++++ llvm/lib/CodeGen/LazyLiveness.cpp | 153 +++++++++++++++++++++++ 2 files changed, 215 insertions(+) create mode 100644 llvm/include/llvm/CodeGen/LazyLiveness.h create mode 100644 llvm/lib/CodeGen/LazyLiveness.cpp diff --git a/llvm/include/llvm/CodeGen/LazyLiveness.h b/llvm/include/llvm/CodeGen/LazyLiveness.h new file mode 100644 index 000000000000..702ba142c5db --- /dev/null +++ b/llvm/include/llvm/CodeGen/LazyLiveness.h @@ -0,0 +1,62 @@ +//===- LazyLiveness.h - Lazy, CFG-invariant liveness information ----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This pass implements a lazy liveness analysis as per "Fast Liveness Checking +// for SSA-form Programs," by Boissinot, et al. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_LAZYLIVENESS_H +#define LLVM_CODEGEN_LAZYLIVENESS_H + +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineDominators.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/SparseBitVector.h" +#include + +namespace llvm { + +class MachineRegisterInfo; + +class LazyLiveness : public MachineFunctionPass { +public: + static char ID; // Pass identification, replacement for typeid + LazyLiveness() : MachineFunctionPass(&ID) { } + + void getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); + AU.addRequired(); + } + + bool runOnMachineFunction(MachineFunction &mf); + + bool vregLiveIntoMBB(unsigned vreg, MachineBasicBlock* MBB); + +private: + void computeBackedgeChain(MachineFunction& mf, MachineBasicBlock* MBB); + + typedef std::pair edge_t; + + MachineRegisterInfo* MRI; + + DenseMap preorder; + std::vector rev_preorder; + DenseMap > rv; + DenseMap > tv; + DenseSet backedges; + SparseBitVector<128> backedge_source; + SparseBitVector<128> backedge_target; + SparseBitVector<128> calculated; +}; + +} + +#endif \ No newline at end of file diff --git a/llvm/lib/CodeGen/LazyLiveness.cpp b/llvm/lib/CodeGen/LazyLiveness.cpp new file mode 100644 index 000000000000..403e0c62f485 --- /dev/null +++ b/llvm/lib/CodeGen/LazyLiveness.cpp @@ -0,0 +1,153 @@ +//===- LazyLiveness.cpp - Lazy, CFG-invariant liveness information --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This pass implements a lazy liveness analysis as per "Fast Liveness Checking +// for SSA-form Programs," by Boissinot, et al. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "lazyliveness" +#include "llvm/CodeGen/LazyLiveness.h" +#include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/PostOrderIterator.h" +using namespace llvm; + +char LazyLiveness::ID = 0; + +void LazyLiveness::computeBackedgeChain(MachineFunction& mf, + MachineBasicBlock* MBB) { + SparseBitVector<128> tmp = rv[MBB]; + tmp.set(preorder[MBB]); + tmp &= backedge_source; + calculated.set(preorder[MBB]); + + for (SparseBitVector<128>::iterator I = tmp.begin(); I != tmp.end(); ++I) { + MachineBasicBlock* SrcMBB = rev_preorder[*I]; + + for (MachineBasicBlock::succ_iterator SI = SrcMBB->succ_begin(); + SI != SrcMBB->succ_end(); ++SI) { + MachineBasicBlock* TgtMBB = *SI; + + if (backedges.count(std::make_pair(SrcMBB, TgtMBB)) && + !rv[MBB].test(preorder[TgtMBB])) { + if (!calculated.test(preorder[TgtMBB])) + computeBackedgeChain(mf, TgtMBB); + + tv[MBB].set(preorder[TgtMBB]); + tv[MBB] |= tv[TgtMBB]; + } + } + + tv[MBB].reset(preorder[MBB]); + } +} + +bool LazyLiveness::runOnMachineFunction(MachineFunction &mf) { + rv.clear(); + tv.clear(); + backedges.clear(); + backedge_source.clear(); + backedge_target.clear(); + calculated.clear(); + preorder.clear(); + + MRI = &mf.getRegInfo(); + + // Step 0: Compute preorder numbering for all MBBs. + unsigned num = 0; + for (df_iterator DI = df_begin(&*mf.begin()); + DI != df_end(&*mf.end()); ++DI) { + preorder[*DI] = num++; + rev_preorder.push_back(*DI); + } + + // Step 1: Compute the transitive closure of the CFG, ignoring backedges. + for (po_iterator POI = po_begin(&*mf.begin()); + POI != po_end(&*mf.begin()); ++POI) { + MachineBasicBlock* MBB = *POI; + SparseBitVector<128>& entry = rv[MBB]; + entry.set(preorder[MBB]); + + for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(); + SI != MBB->succ_end(); ++SI) { + DenseMap >::iterator SII = + rv.find(*SI); + + // Because we're iterating in postorder, any successor that does not yet + // have an rv entry must be on a backedge. + if (SII != rv.end()) { + entry |= SII->second; + } else { + backedges.insert(std::make_pair(MBB, *SI)); + backedge_source.set(preorder[MBB]); + backedge_target.set(preorder[*SI]); + } + } + } + + for (SparseBitVector<128>::iterator I = backedge_source.begin(); + I != backedge_source.end(); ++I) + computeBackedgeChain(mf, rev_preorder[*I]); + + for (po_iterator POI = po_begin(&*mf.begin()), + POE = po_end(&*mf.begin()); POI != POE; ++POI) + if (!backedge_target.test(preorder[*POI])) + for (MachineBasicBlock::succ_iterator SI = (*POI)->succ_begin(); + SI != (*POI)->succ_end(); ++SI) + if (!backedges.count(std::make_pair(*POI, *SI)) && tv.count(*SI)) + tv[*POI]= tv[*SI]; + + for (po_iterator POI = po_begin(&*mf.begin()), + POE = po_end(&*mf.begin()); POI != POE; ++POI) + tv[*POI].set(preorder[*POI]); + + return false; +} + +bool LazyLiveness::vregLiveIntoMBB(unsigned vreg, MachineBasicBlock* MBB) { + MachineDominatorTree& MDT = getAnalysis(); + + MachineBasicBlock* DefMBB = MRI->def_begin(vreg)->getParent(); + unsigned def = preorder[DefMBB]; + unsigned max_dom = 0; + for (df_iterator DI = df_begin(MDT[DefMBB]); + DI != df_end(MDT[DefMBB]); ++DI) + if (preorder[DI->getBlock()] > max_dom) { + max_dom = preorder[(*DI)->getBlock()]; + } + + if (preorder[MBB] <= def || max_dom < preorder[MBB]) + return false; + + SparseBitVector<128>::iterator I = tv[MBB].begin(); + while (I != tv[MBB].end() && *I <= def) ++I; + while (I != tv[MBB].end() && *I < max_dom) { + for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(vreg); + UI != MachineRegisterInfo::use_end(); ++UI) { + MachineBasicBlock* UseMBB = UI->getParent(); + if (rv[rev_preorder[*I]].test(preorder[UseMBB])) + return true; + + unsigned t_dom = 0; + for (df_iterator DI = + df_begin(MDT[rev_preorder[*I]]); + DI != df_end(MDT[rev_preorder[*I]]); ++DI) + if (preorder[DI->getBlock()] > t_dom) { + max_dom = preorder[(*DI)->getBlock()]; + } + I = tv[MBB].begin(); + while (I != tv[MBB].end() && *I < t_dom) ++I; + } + } + + return false; +} \ No newline at end of file