forked from OSchip/llvm-project
Fix SHL_PARTS
Start implementation of integer varargs llvm-svn: 21065
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@ -192,8 +192,16 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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// If the function takes variable number of arguments, make a frame index for
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// the start of the first vararg value... for expansion of llvm.va_start.
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if (F.isVarArg())
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if (F.isVarArg()) {
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VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
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// If this function is vararg, store r4-r10 to their spots on the stack so
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// that they may be loaded by dereferencing va_next
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SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
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SDOperand Val = DAG.getCopyFromReg(PPC::R4, MVT::i32, DAG.getRoot());
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val, Val, FIN);
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DAG.setRoot(Val.getValue(1));
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ArgValues.push_back(Store);
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}
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return ArgValues;
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}
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@ -1352,7 +1360,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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BuildMI(BB, PPC::SRW, 2, Tmp3).addReg(ShiftOpLo).addReg(Tmp1);
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BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
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BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32);
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BuildMI(BB, PPC::SLW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5);
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BuildMI(BB, PPC::SLW, 2, Tmp6).addReg(ShiftOpLo).addReg(Tmp5);
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BuildMI(BB, PPC::OR, 2, Result+1).addReg(Tmp4).addReg(Tmp6);
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BuildMI(BB, PPC::SLW, 2, Result).addReg(ShiftOpLo).addReg(SHReg);
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} else if (ISD::SRL_PARTS == opcode) {
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