forked from OSchip/llvm-project
[IndVars] Widen more comparisons for non-negative induction vars
Summary: If an induction variable is provably non-negative, its sign extension is equal to its zero extension. This means narrow uses like icmp slt iNarrow %indvar, %rhs can be widened into icmp slt iWide zext(%indvar), sext(%rhs) Reviewers: atrick, mcrosier, hfinkel Subscribers: hfinkel, reames, llvm-commits Differential Revision: http://reviews.llvm.org/D12745 llvm-svn: 248045
This commit is contained in:
Sanjoy Das
parent
e8d1c59756
commit
f69d0e3384
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@ -849,6 +849,11 @@ class WidenIV {
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Type *WideType;
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bool IsSigned;
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// True if the narrow induction variable is never negative. Tracking this
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// information lets us use a sign extension instead of a zero extension or
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// vice versa, when profitable and legal.
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bool NeverNegative;
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// Context
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LoopInfo *LI;
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Loop *L;
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@ -871,6 +876,7 @@ public:
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OrigPhi(WI.NarrowIV),
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WideType(WI.WidestNativeType),
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IsSigned(WI.IsSigned),
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NeverNegative(false),
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LI(LInfo),
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L(LI->getLoopFor(OrigPhi->getParent())),
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SE(SEv),
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@ -1082,8 +1088,22 @@ bool WidenIV::WidenLoopCompare(NarrowIVDefUse DU) {
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if (!Cmp)
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return false;
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// Sign of IV user and compare must match.
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if (IsSigned != CmpInst::isSigned(Cmp->getPredicate()))
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// We can legally widen the comparison in the following two cases:
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//
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// - The signedness of the IV extension and comparison match
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//
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// - The narrow IV is always positive (and thus its sign extension is equal
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// to its zero extension). For instance, let's say we're zero extending
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// %narrow for the following use
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//
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// icmp slt i32 %narrow, %val ... (A)
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//
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// and %narrow is always positive. Then
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//
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// (A) == icmp slt i32 sext(%narrow), sext(%val)
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// == icmp slt i32 zext(%narrow), sext(%val)
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if (!(NeverNegative || IsSigned == Cmp->isSigned()))
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return false;
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Value *Op = Cmp->getOperand(Cmp->getOperand(0) == DU.NarrowDef ? 1 : 0);
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@ -1097,7 +1117,7 @@ bool WidenIV::WidenLoopCompare(NarrowIVDefUse DU) {
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// Widen the other operand of the compare, if necessary.
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if (CastWidth < IVWidth) {
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Value *ExtOp = getExtend(Op, WideType, IsSigned, Cmp);
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Value *ExtOp = getExtend(Op, WideType, Cmp->isSigned(), Cmp);
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DU.NarrowUse->replaceUsesOfWith(Op, ExtOp);
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}
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return true;
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@ -1247,6 +1267,9 @@ PHINode *WidenIV::CreateWideIV(SCEVExpander &Rewriter) {
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if (!AddRec)
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return nullptr;
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NeverNegative = SE->isKnownPredicate(ICmpInst::ICMP_SGE, AddRec,
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SE->getConstant(AddRec->getType(), 0));
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// Widen the induction variable expression.
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const SCEV *WideIVExpr = IsSigned ?
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SE->getSignExtendExpr(AddRec, WideType) :
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@ -193,3 +193,131 @@ for.body:
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for.end:
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ret i32 %sum.0
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}
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define i32 @test6(i32* %a, i32 %b) {
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; CHECK-LABEL: @test6(
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; CHECK: [[B_SEXT:%[a-z0-9]+]] = sext i32 %b to i64
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; CHECK: for.cond:
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; CHECK: icmp sle i64 %indvars.iv, [[B_SEXT]]
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entry:
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br label %for.cond
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for.cond:
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%sum.0 = phi i32 [ 0, %entry ], [ %add, %for.body ]
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%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%cmp = icmp sle i32 %i.0, %b
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br i1 %cmp, label %for.body, label %for.end
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for.body:
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%idxprom = zext i32 %i.0 to i64
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%arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom
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%0 = load i32, i32* %arrayidx, align 4
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%add = add nsw i32 %sum.0, %0
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%inc = add nsw i32 %i.0, 1
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br label %for.cond
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for.end:
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ret i32 %sum.0
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}
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define i32 @test7(i32* %a, i32 %b) {
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; CHECK-LABEL: @test7(
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; CHECK: [[B_ZEXT:%[a-z0-9]+]] = zext i32 %b to i64
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; CHECK: [[B_SEXT:%[a-z0-9]+]] = sext i32 %b to i64
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; CHECK: for.cond:
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; CHECK: icmp ule i64 %indvars.iv, [[B_ZEXT]]
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; CHECK: for.body:
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; CHECK: icmp sle i64 %indvars.iv, [[B_SEXT]]
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entry:
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br label %for.cond
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for.cond:
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%sum.0 = phi i32 [ 0, %entry ], [ %add, %for.body ]
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%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%cmp = icmp ule i32 %i.0, %b
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br i1 %cmp, label %for.body, label %for.end
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for.body:
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%idxprom = sext i32 %i.0 to i64
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%arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom
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%0 = load i32, i32* %arrayidx, align 4
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%add = add nsw i32 %sum.0, %0
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%inc = add nsw i32 %i.0, 1
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%cmp2 = icmp sle i32 %i.0, %b
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br i1 %cmp2, label %for.cond, label %for.end
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for.end:
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ret i32 %sum.0
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}
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define i32 @test8(i32* %a, i32 %b, i32 %init) {
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; CHECK-LABEL: @test8(
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; CHECK: [[INIT_SEXT:%[a-z0-9]+]] = sext i32 %init to i64
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; CHECK: [[B_ZEXT:%[a-z0-9]+]] = zext i32 %b to i64
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; CHECK: for.cond:
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; Note: %indvars.iv is the sign extension of %i.0
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; CHECK: %indvars.iv = phi i64 [ [[INIT_SEXT]], %for.cond.preheader ], [ %indvars.iv.next, %for.body ]
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; CHECK: icmp ule i64 %indvars.iv, [[B_ZEXT]]
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entry:
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%e = icmp sgt i32 %init, 0
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br i1 %e, label %for.cond, label %leave
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for.cond:
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%sum.0 = phi i32 [ 0, %entry ], [ %add, %for.body ]
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%i.0 = phi i32 [ %init, %entry ], [ %inc, %for.body ]
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%cmp = icmp ule i32 %i.0, %b
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br i1 %cmp, label %for.body, label %for.end
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for.body:
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%idxprom = sext i32 %i.0 to i64
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%arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom
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%0 = load i32, i32* %arrayidx, align 4
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%add = add nsw i32 %sum.0, %0
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%inc = add nsw i32 %i.0, 1
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%cmp2 = icmp slt i32 0, %inc
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br i1 %cmp2, label %for.cond, label %for.end
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for.end:
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ret i32 %sum.0
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leave:
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ret i32 0
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}
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define i32 @test9(i32* %a, i32 %b, i32 %init) {
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; CHECK-LABEL: @test9(
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; CHECK: [[INIT_ZEXT:%[a-z0-9]+]] = zext i32 %init to i64
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; CHECK: [[B_SEXT:%[a-z0-9]+]] = sext i32 %b to i64
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; CHECK: for.cond:
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; Note: %indvars.iv is the zero extension of %i.0
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; CHECK: %indvars.iv = phi i64 [ [[INIT_ZEXT]], %for.cond.preheader ], [ %indvars.iv.next, %for.body ]
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; CHECK: icmp slt i64 %indvars.iv, [[B_SEXT]]
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entry:
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%e = icmp sgt i32 %init, 0
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br i1 %e, label %for.cond, label %leave
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for.cond:
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%sum.0 = phi i32 [ 0, %entry ], [ %add, %for.body ]
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%i.0 = phi i32 [ %init, %entry ], [ %inc, %for.body ]
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%cmp = icmp slt i32 %i.0, %b
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br i1 %cmp, label %for.body, label %for.end
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for.body:
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%idxprom = zext i32 %i.0 to i64
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%arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom
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%0 = load i32, i32* %arrayidx, align 4
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%add = add nsw i32 %sum.0, %0
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%inc = add nsw i32 %i.0, 1
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%cmp2 = icmp slt i32 0, %inc
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br i1 %cmp2, label %for.cond, label %for.end
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for.end:
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ret i32 %sum.0
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leave:
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ret i32 0
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}
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